MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 627

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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15.4.7
The QTEST register is used for factory testing of the MCU.
15.4.8
The QDSCI_ILI and QSPI_IL registers determine the interrupt level requested by the QSMCM. The two
SCI submodules (DSCI) share a 5-bit interrupt level field, ILDSCI. The QSPI uses a separate field,
ILQSPI. The level value is used to determine which interrupt is serviced first when two or more modules
or external peripherals simultaneously request an interrupt. The user can select among 32 levels. This
register can be accessed only when the CPU is in supervisor mode.
Freescale Semiconductor
SRESET
12:15
Bits
9:11
Bits
8:15
Field
Addr
2:7
0:2
3:7
0
1
8
QSMCM Test Register (QTEST)
QSMCM Interrupt Level Registers (QDSCI_IL, QSPI_IL)
MSB
0
ILDSCI
Name
STOP
SUPV
Name
FRZ1
Figure 15-5. QSM2 Dual SCI Interrupt Level Register (QDSCI_IL)
1
2
Stop enable. Refer to
0 Normal clock operation
1 Internal clocks stopped
Freeze1 bit. Refer to
0 Ignore the FREEZE signal
1 Halt the QSMCM (on transfer boundary)
Reserved
Supervisor / Unrestricted. Refer to
0 Assigned registers are unrestricted (user access allowed)
1 Assigned registers are restricted (only supervisor access allowed)
Reserved
Reserved. These bits are used for the IARB (interrupt arbitration ID) field in QSM
implementations that use hardware interrupt arbitration.
Reserved
Interrupt level of Dual SCIs
00000lowest interrupt level request (level 0)
11111highest interrupt level request (level 31)
Reserved
Table 15-4. QSMCMMCR Bit Descriptions
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 15-5. QDSCI_IL Bit Descriptions
3
4
ILDSCI
5
Section 15.4.2, “Freeze
Section 15.4.1, “Low-Power Stop
0000_0000_0000_0000
6
0x30 5004
Section 15.4.3, “Access
7
Description
Description
8
Operation.”
9
10
Operation.”
Queued Serial Multi-Channel Module
Protection.”
11
12
13
14
LSB
15
15-9

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