MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 641

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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15.6.2.1
Data received by the QSPI is stored in this segment, to be read by the CPU. Data stored in the receive RAM
is right-justified, (i.e., the least significant bit is always in the right-most bit position within the word
regardless of the serial transfer length). Unused bits in a receive queue entry are set to zero by the QSPI
upon completion of the individual queue entry. The CPU can access the data using byte, half-word, or word
addressing.
The CPTQP value in SPSR shows which queue entries have been executed. The CPU uses this information
to determine which locations in receive RAM contain valid data before reading them.
15.6.2.2
Data that is to be transmitted by the QSPI is stored in this segment. The CPU normally writes one word of
data into this segment for each queue command to be executed. If the corresponding peripheral, such as a
serial input port, is used solely to input data, then this segment does not need to be initialized.
Data must be written to transmit RAM in a right-justified format. The QSPI cannot modify information in
the transmit RAM. The QSPI copies the information to its data serializer for transmission. Information
remains in transmit RAM until overwritten.
15.6.2.3
Command RAM is used by the QSPI in master mode. The CPU writes one byte of control information to
this segment for each QSPI command to be executed. The QSPI cannot modify information in command
RAM.
Command RAM consists of 32 bytes. Each byte is divided into two fields. The peripheral chip-select field,
enables peripherals for transfer. The command control field provides transfer options.
A maximum of 32 commands can be in the queue. These bytes are assigned an address from 0x00 to 0x1F.
Queue execution by the QSPI proceeds from the address in NEWQP through the address in ENDQP. (Both
of these fields are in SPCR2.)
Freescale Semiconductor
or 0x30 5540
or 0x30 557F
0x30 5140
0x30 517F
Receive RAM
Transmit RAM
Command RAM
Half-Word
Receive
RAM
RRD
RRE
RRF
RR1
RR2
RR0
MPC561/MPC563 Reference Manual, Rev. 1.2
oe 0x30 55BF
or 0x30 5580
Figure 15-16. QSPI RAM
0x30 51BF
0x30 5180
Half-Word
Transmit
RAM
TRD
TRE
TR0
TR1
TR2
TRF
or 0x30 55DF
or 0x30 55C0
0x30 51DF
0x30 51C0
Queued Serial Multi-Channel Module
Command
RAM
CRD
CRE
CRF
CR0
CR1
CR2
Byte
15-23

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