MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 679

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

15.8.2.2
Freescale Semiconductor
12:15
Bits
Bits
SRESET
0:2
10
11
3
4
Field
Addr
QSCI1 Status Register (QSCI1SR)
QTWE
Name
QTSZ
Name
QTHF
QOR
QRE
MSB
—
0
000
—
1
Queue receive enable. When set, the receive queue is enabled and the RDRF bit should be
ignored by software. When clear, the SCI1 functions as described in the previous sections and
the bits related to the queue (Section 5.5 and its subsections) should be ignored by software with
the exception of QRE.
0 Receive queue is disabled
1 Receive queue is enabled
Queue transmit wrap enable. When set, the transmit queue is allowed to restart transmitting from
the top of the queue after reaching the bottom of the queue. After each wrap of the queue, QTWE
is cleared by hardware.
0 Transmit queue wrap feature is disabled
1 Transmit queue wrap feature is enabled
Queue transfer size. The QTSZ bits allow programming the number of data frames to be
transmitted. From 1 (QTSZ = 0b0000) to 16 (QTSZ = 0b1111) data frames can be specified.
QTSZ is loaded into QPEND initially or when a wrap occurs.
Reserved
Receiver queue overrun error. The QOR is set when a new data frame is ready to be transferred
from the SC1DR to the queue and the queue is already full (QTHF or QBHF are still set). Data
transfer is inhibited until QOR is cleared. Previous data transferred to the queue remains valid.
Additional data received during a queue overrun condition is not lost provided the receive queue
is re-enabled before OR (SC1SR) is set. The OR flag is set when a new data frame is received
in the shifter but the data register (SC1DR) is still full. The data in the shifter that generated the
OR assertion is overwritten by the next received data frame, but the data in the SC1DR is not lost.
0 The queue is empty before valid data is in the SC1DR
1 The queue is not empty when valid data is in the SC1DR
Receiver queue top-half full. QTHF is set when the receive queue locations SCRQ[0:7] are
completely filled with new data received via the serial shifter. QTHF is cleared when register
QSCI1SR is read with QTHF set, followed by a write of QTHF to zero.
0 The queue locations SCRQ[0:7] are partially filled with newly received data or is empty
1 The queue locations SCRQ[0:7] are completely full of newly received data
Table 15-32. QSCI1CR Bit Descriptions (continued)
2
Figure 15-32. QSCI1 Status Register (QSCI1SR)
QOR QTHF QBHF QTHE QBHE
MPC561/MPC563 Reference Manual, Rev. 1.2
0
3
Table 15-33. QSCI1SR Bit Descriptions
1
4
1
5
1
6
0x30 502A
Description
Description
7
1
8
QRPNT
9
0000
10
Queued Serial Multi-Channel Module
11
12
QPEND
13
0000
14
LSB
15
15-61