MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 712

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

CAN 2.0B Controller Module
After engaging one of the mechanisms to place the TouCAN in debug mode, the FRZACK bit must be set
before accessing any other registers in the TouCAN; otherwise unpredictable operation may occur.
To exit debug mode, the IMB3 FREEZE line must be negated or the HALT bit in CANMCR must be
cleared.
Once debug mode is exited, the TouCAN resynchronizes with the CAN bus by waiting for 11 consecutive
recessive bits before beginning to participate in CAN bus communication.
16.5.2
Before entering low-power stop mode, the TouCAN waits for the CAN bus to be in an idle state, or for the
third bit of intermission to be recessive. The TouCAN then waits for the completion of all internal activity
(except in the CAN bus interface) to be complete. Then the following events occur:
To exit low-power stop mode:
When the TouCAN is in low-power stop mode, a recessive to dominant transition on the CAN bus causes
the WAKEINT bit in the error and status register (ESTAT) to be set. This event generates an interrupt if
the WAKEMSK bit in CANMCR is set.
Consider the following notes regarding low-power stop mode:
16-18
•
•
•
•
•
•
•
•
•
•
•
•
The TouCAN stops transmitting or receiving frames
The prescaler is disabled, thus halting all CAN bus communication
The TouCAN ignores its Rx signals and drives its Tx signals as recessive
The TouCAN loses synchronization with the CAN bus and the NOTRDY and FRZACK bits in
CANMCR are set
The CPU is allowed to read and write the error counter registers
The TouCAN shuts down its clocks, stopping most internal circuits, thus achieving maximum
power savings
The bus interface unit continues to operate, allowing the CPU to access the module configuration
register
The TouCAN ignores its Rx signals and drives its Tx signals as recessive
The TouCAN loses synchronization with the CAN bus, and the STOPACK and NOTRDY bits in
the module configuration register are set
Reset the TouCAN either by asserting one of the IMB3 reset lines or by asserting the SOFTRST
bit CANMCR
Clear the STOP bit in CANMCR
The TouCAN module can optionally exit low-power stop mode via the self wake mechanism. If
the SELFWAKE bit in CANMCR was set at the time the TouCAN entered stop mode, then upon
detection of a recessive to dominant transition on the CAN bus, the TouCAN clears the STOP bit
in CANMCR and its clocks begin running.
Low-Power Stop Mode
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor