MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 726

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

CAN 2.0B Controller Module
16.7.10 Receive Buffer 14 Mask Registers (RX14MSKHI, RX14MSKLO)
The receive buffer 14 mask registers have the same structure as the receive global mask registers and are
used to mask buffer 14.
16-32
SRESET
SRESET
Bits
0:31
Bits
0:31
Field MID2
Field MID1
Addr
Figure 16-17. Receive Buffer 14 Mask Registers: High (RX14MSKHI), Low (RX14MSKLO)
MSB
16
8
1
4
1
0
Name
Name
MIDx
MIDx
MID2
MID1
17
7
1
3
1
1
0x30 7096 (Rx14MSKLO_A); 0x30 7496 (Rx14MSKLO_B); 0x30 7896 (Rx14MSKLO_C)
0x30 7094 (Rx14MSKHI_A); 0x30 7494 (Rx14MSKHI_B); 0x30 7894 (Rx14MSKHI_C);
MID2
MID1
Table 16-21. RX14MSKHI, RX14MSKLO Field Descriptions
The receive global mask registers use four bytes. The mask bits are applied to all
receive-identifiers, excluding receive-buffers 14 and 15, which have their own specific mask
registers.
Base ID mask bits MID[28:18] are used to mask standard or extended format frames.
Extended ID bits MID[17:0] are used to mask only extended format frames.
The RTR/SRR bit of a received frame is never compared to the corresponding bit in the
message buffer ID field. However, remote request frames (RTR = 1) once received, are never
stored into the message buffers. RTR mask bit locations in the mask registers (bits 11 and
31) are always zero, regardless of any write to these bits.
The IDE bit of a received frame is always compared to determine if the message contains a
standard or extended identifier. Its location in the mask registers (bit 12) is always one,
regardless of any write to this bit.
The receive buffer 14 mask registers use 4 bytes.
Base ID mask bits MID[28:18] are used to mask standard or extended format frames.
Extended ID bits MID[17:0] are used to mask only extended format frames.
The RTR/SRR bit of a received frame is never compared to the corresponding bit in the
message buffer ID field. However, remote request frames (RTR = 1) once received, are never
stored into the message buffers. RTR mask bit locations in the mask registers (bits 11 and
31) are always zero, regardless of any write to these bits.
The IDE bit of a received frame is always compared to determine if the message contains a
standard or extended identifier. Its location in the mask registers (bit 12) is always one,
regardless of any write to this bit.
18
6
1
2
1
Table 16-20. RXGMSKHI, RXGMSKLO Bit Descriptions
2
MID2
MID1
19
5
1
1
1
3
MPC561/MPC563 Reference Manual, Rev. 1.2
MID2
MID1
20
4
1
0
1
4
MID2
MID9 MID8 MID7 MID6 MID5 MID4 MID3 MID2 MID
21
5
3
1
1
MID2
22
2
1
1
6
MID2
23
1
1
1
7
Description
Description
MID2
24
0
1
1
8
MID1
25
9
1
1
9
MID1
10
26
8
1
1
11
27
0
0
1
12
28
1
1
1
Freescale Semiconductor
MID
17
13
29
1
1
1
MID
MID
16
14
30
1
0
1
MID
LSB
15
15
31
1
0
0