MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 774

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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Modular Input/Output Subsystem (MIOS14)
17.9.6.3
17-42
0:15
Bits
SRESET
Field
Addr
Name
AR
MDASM Data B (MDASMBR) Register
MSB
0
MDASMAR is the data register associated with channel A; its use varies with the different modes of
operation:
DIS mode: MDASMAR can be accessed to prepare a value for a subsequent mode selection.
IPWM mode: MDASMAR contains the captured value corresponding to the trailing edge of the measured
pulse.
IPM and IC modes: MDASMAR contains the captured value corresponding to the most recently detected
dedicated edge (rising or falling edge).
OCB and OCAB modes: MDASMAR is loaded with the value corresponding to the leading edge of the
pulse to be generated. Writing to MDASMAR in the OCB and OCAB modes also enables the
corresponding channel A comparator until the next successful comparison.
OPWM mode: MDASMAR is loaded with the value corresponding to the leading edge of the PWM pulse
to be generated.
NOTE: In IC, IPM, or IPWM mode, when a read to register A or B occurs at the same time as a counter
bus capture into that register and the counter bus is changing value, then the counter bus capture to that
register is delayed.
1
2
Figure 17-23. MDASM DataB Register (MDASMBR)
3
Table 17-19. MDASMAR Bit Descriptions
MPC561/MPC563 Reference Manual, Rev. 1.2
0x30 60DA, 0x30 60E2, 0x30 60EA, 0x30 60F2, 0x30 60FA
0x30 605A, 0x30 6062, 0x30 606A, 0x30 6072, 0x30 607A,
4
5
6
Undefined
7
Description
BR
8
9
10
11
12
Freescale Semiconductor
13
14
LSB
15

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