MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 830

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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Peripheral Pin Multiplexing (PPM) Module
18.4.12
SCALE_TCLK_REG is used to set the rate of the PPM_TCLK that provides the timing for data transfer
into and out of the PPM module. The PPM_TCLK frequency is derived from the system clock, F
PPM_TCLK is software programmable using the following formula:
The range of PPM_TCLK frequencies available is:
18-24
SRESET
Bits
9:15
0:8
Field
Addr
F
PPM_TCLK
Scale Transmit Clock Register (SCALE_TCLK_REG)
MSB
SHORT_CH_REG
0
Data transmitted
Data transmitted
Register Name
TX_DATA[0:15]
SCT[6:0]
Name
Figure 18-27. Scale Transmit Clock Register (SCALE_TCLK_REG)
1
= F
Table 18-11. Examples of the SHORT_CH Bits (continued)
SYSCLK
2
Table 18-13. SCALE_TCLK_REG Bit Descriptions
Reserved
Determines the frequency of PPM_TCLK.
Writing to SCT[6:0] while the PPM is enabled will cause an irregular PPM cycle to
occur.
• SCT[6:0] = 0 F
• SCT[6:0] = 1 to 127 F
RESERVED
3
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 18-12. SCALE_TCLK Frequencies
F
/ (2 * SCT[6:0])
SYSCLK
Minimum
4
Contents
Register
0x00FF
0x303C
0x3034
0x1234
/256
5
SYSCLK
0000_0000_0000_0000
Example 3
6
SYSCLK
/256
0x30 5C2A
0b 0011 0000 0011 0100
SHORT_CH[7:0] = 1, therefore bits (TX_DATA[1, 3, 5,
7, 9, 11, 13, 15] are enabled for re-transmission.
0b 0001 0010 0011 0100
Underlines show bits to be re-transmitted
0b 0011 0000 0011 1100
7
/ (2 * SCT[6:0])
8
Maximum
F
Description
SYSCLK
9
/2
10
Comments
11
SCT[6:0]
12
Freescale Semiconductor
13
14
SYSCLK
LSB
15
.

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