MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 833

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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19.2.4
The microengine is composed of a control store and an execution unit. Control-store ROM holds the
microcode for each factory-masked time function. When assigned to a channel by the scheduler, the
execution unit executes microcode for a function assigned to that channel by the CPU. Microcode can also
be executed from the dual-port RAM (DPTRAM) module instead of the control store. The DPTRAM
allows emulation and development of custom TPU microcode without the generation of a microcode ROM
mask. Refer to
19.2.5
The host interface registers allow communication between the CPU and the TPU3, both before and during
execution of a time function. The registers are accessible from the IMB through the TPU3 bus interface
unit. Refer to
19.2.6
Parameter RAM occupies 256 bytes at the top of the system address map. Channel parameters are
organized as 128 16-bit words. Channels zero through 15 each have eight parameters. The parameter RAM
address map in
memory.
The CPU specifies function parameters by writing to the appropriate RAM address. The TPU3 reads the
RAM to determine channel operation. The TPU3 can also store information to be read by the CPU in the
parameter RAM. Detailed descriptions of the parameters required by each time function are beyond the
scope of this manual. Refer to the TPU Reference Manual (TPURM/AD), included in the TPU Literature
Package (TPULITPAK/D) for more information.
19.3
All TPU3 functions are related to one of the two 16-bit time bases. Functions are synthesized by combining
sequences of match events and capture events. Because the primitives are implemented in hardware, the
TPU3 can determine precisely when a match or capture event occurs, and respond rapidly. An event
register for each channel provides for simultaneous match/capture event occurrences on all channels.
When a match or input capture event requiring service occurs, the affected channel generates a service
request to the scheduler. The scheduler determines the priority of the request and assigns the channel to
the microengine at the first available time. The microengine performs the function defined by the content
of the control store or emulation RAM, using parameters from the parameter RAM.
19.3.1
Match and capture events are handled by independent channel hardware. This provides an event accuracy
of one time-base clock period, regardless of the number of channels that are active. An event normally
causes a channel to request service. The time needed to respond to and service an event is determined by
which channels and the number of channels requesting service, the relative priorities of the channels
requesting service, and the microcode execution time of the active functions. Worst-case event service
Freescale Semiconductor
TPU Operation
Microengine
Host Interface
Parameter RAM
Event Timing
Section 19.4, “Programming
Section 19.3.6, “Emulation
Section 19.4.15, “TPU3 Parameter
MPC561/MPC563 Reference Manual, Rev. 1.2
Support” for more information.
Model” for register bit/field definitions and address mapping.
RAM,” shows how parameter words are organized in
Time Processor Unit 3
19-3

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