MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 880

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

1
CDR3 Flash (UC3F) EEPROM
During reset, the has configuration bit (HC) and the USIU configure the UC3F EEPROM module to
provide UC3FCFIG. If HC = 0 and the USIU requests internal configuration during reset the reset
configuration word will be provided by UC3FCFIG.
The default reset state of the UC3FCFIG after an erase operation of the UC3F module is no configuration
word available (HC = 1).
21-18
17:18
24:25
26:27
28:30
Bits
This bit is available only on the MPC564.
16
19
20
21
22
23
31
EXC_COMP
EN_COMP
PRPM
OERC
Name
ETRE
DME
ISB
HC
SC
—
—
1
1
Peripheral mode enable — This bit determines if the chip is in peripheral mode. A detailed description
is in
Single chip select — This field defines the mode of the MPC563.
00 Extended chip, 32 bits data
01 Extended chip, 16 bits data
10 Single chip and show cycles (address)
11 Single chip
See
Exception table relocation enable — This field defines whether the Exception Table Relocation feature
in the BBC is enabled or disabled. The default state for this field is disabled. For more details, see
Table
Has configuration – This bit determines if the Flash Reset Configuration word is valid.
0 The Flash shadow row contains a valid Reset Configuration Word
1 The Flash shadow row does not contain a valid Reset Configuration Word
Enable compression — This bit enables the operation of the MPC564 with compressed code. See
Table
Exception compression — This bit determines the operation of the MPC564 with exceptions.
0 indicates the exceptions are all non-compressed. See
1 the MPC564 assumes that ALL the exception routines are in compressed code.
Reserved. This bit must be programmed low in the reset configuration word.
Other exceptions relocation control — These bits effect only if ETRE was enabled.
Relocation offset:
00 Offset 0
01 Offset 64 Kbytes
10 Offset 512 Kbytes
11 Offset to 0x003F E000
See
Reserved
Internal space base select — This field defines the initial value of the ISB field in the IMMR register. A
detailed description is in
start at address 0x0000_0000. This bit must not be high in the reset configuration word.
Dual mapping enable — This bit determines whether Dual mapping of the internal Flash is enabled. For
a detailed description refer to
0 Dual mapping disabled
1 Dual mapping enabled
Table
Table
Table
4-4.
4-4.
6-13. The default value is no peripheral mode enabled.
6-10.
4-2.
Table 21-6. RCW Bit Descriptions (continued)
MPC561/MPC563 Reference Manual, Rev. 1.2
Table
Table
6-12. The default state is that the internal memory map is mapped to
10-11. The default state is that dual mapping is disabled.
Description
Table
4-4.
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