MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 938

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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Development Support
The debug interface is enabled by:
or
The state of this pin is sampled three clocks before the negation of SRESET.
If the DSCK pin is sampled negated, debug mode is disabled until a subsequent reset when the DSCK pin
is sampled in the asserted state. When debug mode is disabled the internal watchpoint/breakpoint hardware
will still be operational and may be used by a software monitor program for debugging purposes.
When debug mode is disabled, all development support registers (see list in
the supervisor code (MSR[PR] = 0) and can be used by a monitor debugger software. However, the
processor never enters debug mode and, therefore, the exception cause register (ECR) and the debug
enable register (DER) are used only for asserting and negating the freeze signal. For more information on
the software monitor debugger support refer to
When debug mode is enabled, all development support registers are accessible only when the CPU is in
debug mode. Therefore, even supervisor code that may be still under debug cannot prevent the CPU from
entering debug mode. The development system has full control of all development support features of the
CPU through the development port. Refer to
23.3.1.2
Entering debug mode can be a result of a number of events. All events have a programmable enable bit to
selectively decide which events result in debug mode entry and which in regular interrupt handling.
23-24
JCOMP/RSTI
PORESET
Configuration
holding JCOMP/RSTI low while HRESET is asserted and then entering BDM (DSCK=high at
HRESET negation)
configuring READI to be disabled (EVTI=high at RSTI negation) and then entering BDM
(DSCK=high at HRESET negation)
Entering Debug Mode
Because SRESET negation is done by an external pull up resistor any
reference here to SRESET negation time refers to the time the
MPC561/MPC563 releases SRESET. If the actual negation is slow due to a
large resistor, set up time for the debug port signals should be set
accordingly.
(Low)
JTAG disabled
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure 23-7. BDM Mode Selection
Table
READI Disabled/ BDM can be enabled/entered
Section 23.5, “Software Monitor Debugger
NOTE
23-16.
Table
23-14) are accessible to
Freescale Semiconductor
T
Support.”

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