MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 952

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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Development Support
For large blocks of data this sequence may take significant time to complete. The “fast download
procedure” of the debug port may be used to reduce this time. This time reduction is achieved by
eliminating the need to transfer the instructions in the loop to the debug port. The only transactions needed
are those required to transfer the data to be placed in system memory.
illustrate the time benefit of the “fast download procedure”.
The sequence of the instructions used in the “fast download procedure” is the one illustrated in
Figure 23-12
procedure” command is issued to the debug port.
Note that, the internal general purpose register 31 is used for temporary storage data value. Before
beginning the “fast download procedure” by the “start download procedure command”, The value of the
first memory block address, – 4, must be written to the general purpose register 30.
To end a download procedure, an “end download procedure” command should be issued to the debug port,
and then, additional DATA transaction should be sent by the development tool. This data word will NOT
be placed into the system memory, but it is needed to stop the procedure gracefully.
23.5
When in debug mode disable, a software monitor debugger can make use of all of the development support
features defined in the CPU. When debug mode is disabled all events result in regular interrupt handling,
i.e. the processor resumes execution in the corresponding interrupt handler. The exception cause register
(ECR) and the debug enable register (DER) only influence the assertion and negation of the freeze signal.
23.5.1
The internal freeze signal is connected to all relevant internal modules. These modules can be programmed
to stop all operations in response to the assertion of the freeze signal. In order to enable a software monitor
debugger to broadcast the fact that the debug software is now executed, it is possible to assert and negate
the internal freeze signal also when debug mode is disabled.
23-38
Internal
Activity
Internal
Activity
External
Transaction
External
Transaction
Software Monitor Debugger Support
Freeze Indication
with RX = r31 and RY = r30. This sequence is repeated infinitely until the “end download
MFSPR
Figure 23-13. Slow Download Procedure Loop
Figure 23-14. Fast Download Procedure Loop
MPC561/MPC563 Reference Manual, Rev. 1.2
DATA
DATA
Figure 23-13
STWU
and
Freescale Semiconductor
Figure 23-14

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