MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 953

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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The assertion and negation of the freeze signal when in debug mode disable is controlled by the exception
cause register (ECR) and the debug enable register (DER) as described in
the freeze signal the software needs to program the relevant bits in the debug enable register (DER). In
order to negate the freeze line the software needs to read the exception cause register (ECR) in order to
clear it and perform an rfi instruction.
If the exception cause register (ECR) is not cleared before the rfi is performed the freeze signal is not
negated. Therefore it is possible to nest inside a software monitor debugger without affecting the value of
the freeze line although rfi may be performed a few times. Only before the last rfi the software needs to
clear the exception cause register (ECR).
The above mechanism enables the software to accurately control the assertion and the negation of the
freeze signal.
23.6
Table 23-14
sections,
“Development Port Data Register
the mtspr and mfspr instructions.
Freescale Semiconductor
Section 23.6.2, “Comparator A–D Value Registers
Development Support Registers
lists the registers used for development support in SPR number order, and the register
SPR Number
(Decimal)
144
145
146
147
148
149
150
151
152
153
Table 23-14. Development Support Programming Model
Comparator A Value Register (CMPA)
See
Comparator B Value Register (CMPB)
See
Comparator C Value Register (CMPC)
See
Comparator D Value Register (CMPD)
See
Exception Cause Register (ECR)
See
Debug Enable Register (DER)
See
Breakpoint Counter A Value and Control Register (COUNTA)
See
Breakpoint Counter B Value and Control Register (COUNTB)
See
Comparator E Value Register (CMPE)
See
Comparator F Value Register (CMPF)
See
MPC561/MPC563 Reference Manual, Rev. 1.2
(DPDR),” follow the same SPR order. The registers are accessed with
Table 23-17
Table 23-17
Table 23-17
Table 23-17
Table 23-18
Table 23-19
Table 23-20
Table 23-21
Table 23-22
Table 23-22
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
Name
(CMPA–CMPD)” through
Figure
23-6. In order to assert
Section 23.6.13,
Development Support
23-39

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