MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 975

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Freescale Semiconductor
Instruction Taken
Instruction Retire
ICTRL
Ownership Trace
Message (OTM)
Public Messages
RCPU
READI
READI signals
RPM
run-time
Sequential Instruction
Snooping
Standard
Superfield
Show Cycle
Transfer Code (TCODE) Message header that identifies the number and/or size of packets to be transferred, and how
TCK / DSCK / MCKI
TDI / DSDI / MDI0
TDO / DSDO / MDO0
Upload
VSYNC
VF
VFLS
Term
An instruction is taken after it has been issued and recognized by the appropriate execution
unit. All resources to perform the instruction are ready, and the processor begins to execute it.
Completion of the instruction issue, execution and writeback stages. An instruction is ready
to be retired if it completes without generating an exception and all instructions ahead of it in
history buffer have completed without generating an exception.
Instruction bus support control register (Refer to
Visibility of process/function that is currently executing.
Messages on the auxiliary signals for accomplishing common visibility and controllability
requirements e.g. DRM and DWM.
Processor that implements the PowerPC-based architecture used in the Freescale MPC500
family of microcontrollers.
Real time Embedded Applications Development Interface.
Refers to IEEE-ISTO 5001 auxiliary port.
Reduced Port Mode. This is the reduced port mode for READI.
RCPU is executing program code in normal mode
Any instruction other than a flow-control instruction or isync.
Monitoring addresses driven by a bus master to detect the need for coherency actions.
The phrase “according to the standard” implies according the IEEE-ISTO 5001 - 1999.
One or more message “fields” delimited by MSEO/MSEI assertion/negation.
The information transmitted between “start-message” and “end-packet” states.
An internal access (e.g., to an internal memory) reflected on the external bus using a
special cycle (marked with a dedicated transfer code). For an internal memory “hit,” an
address-only bus cycle is generated; for an internal memory “miss,” a complete bus cycle is
generated.
to interpret each of the packets.
Multiplexed signal: JTAG Clock or Development Port Clock. MCKI is a READI signal on the
MPC561/MPC563
Multiplexed signal: JTAG Data In or Development Port Serial Data In. MDI0 is a READI signal
on the MPC561/MPC563.
Multiplexed signal: JTAG Data Out or Development Port Serial Data Out. MDO0 is a READI
signal on the MPC561/MPC563
Device sends information to the tool.
Internal RCPU signal
Internal RCPU signal which indicates instruction queue status.
Internal RCPU signal which indicates history buffer flush status.
Table 24-3. Terms and Definitions (continued)
MPC561/MPC563 Reference Manual, Rev. 1.2
Description
Table
23.6.11)
READI Module
24-7