MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 983

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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24.6.1.8
The UDI register, a 34-bit register, is used to store the data to be written for block write access, and the
data read for read (single and block) accesses.
Freescale Semiconductor
RCPU
27:28
29:60
61:62
64:79
Bits
63
Nexus
52:51
50:19
18:17
Upload/Download Information Register (UDI)
Bits
15:0
16
Table 24-11. RWA Read/Write Access Bit Descriptions (continued)
Name
MAP
CNT
PRV
WD
SZ
The word size (SZ) field can be configured to allow 32-bit, 16-bit, or 8-bit read/write
accesses. If the field is configured to one of the reserved states, its action reverts to
that of the default state.
00 32-bit
01 16-bit
10 8-bit
11 Reserved
Write data (WD) bits contain the data to be written. For a read access, the data stored
is a don’t care.
The Privilege Attribute Field can be configured to select different read/write access
attributes.
00 User Data
01 User Instruction
10 Supervisor Data
11 Supervisor Instruction
The Map Select Field can be configured to allow access to multiple memory maps.
The primary processor memory map (MAP equal to 0b0) is designated as the default.
The secondary memory map (MAP equal to 0b1) can be set to select the MPC500
special purpose registers.
0 Primary memory map
1 Secondary memory map (PPC Special Purpose Registers)
The Access Count Field can be configured to indicate the number of accesses of word
size (defined in SZ field). The CNT value is used to increment the specified address
in the RWAD field for block read/write accesses.
For a single read/write access, the CNT value should equal to 0x0000. A 64-Kbyte
block read/write access can be performed by configuring the CNT bits as 0xFFFF. If
a user wants to terminate a block read or write access which has not completed, the
CNT bits should be reset.
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 24-12
gives a description of the register bits.
Description
READI Module
24-15

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