ATTINY4-TSHR Atmel, ATTINY4-TSHR Datasheet - Page 79
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ATTINY4-TSHR
Manufacturer Part Number
ATTINY4-TSHR
Description
IC MCU AVR 512B FLASH SOT-23-6
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY10-TSHR.pdf
(169 pages)
Specifications of ATTINY4-TSHR
Package / Case
SOT-23-6
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
12MHz
Number Of I /o
4
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32 x 8
Program Memory Size
512B (512 x 8)
Oscillator Type
Internal
Peripherals
POR, PWM, WDT
Core Size
8-Bit
Controller Family/series
ATtiny
No. Of I/o's
4
Ram Memory Size
32Byte
Cpu Speed
12MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
ATTINY4x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
32 B
Interface Type
ISP
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
4
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
Package
6SOT-23
Device Core
AVR
Family Name
ATtiny
Maximum Speed
12 MHz
Operating Supply Voltage
2.5|3.3|5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY4-TSHR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
11.11.7
11.11.8
8127D–AVR–02/10
ICR0H and ICR0L – Input Capture Register 0
TIMSK0 – Timer/Counter Interrupt Mask Register 0
8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-
bit registers. See
The Input Capture is updated with the counter (TCNT0) value each time an event occurs on the
ICP0 pin (or optionally on the Analog Comparator output for Timer/Counter0). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit
registers.
• Bits 7:6, 4:3 – Reserved Bits
These bits are reserved for future use. For ensuring compatibility with future devices, these bits
must be written to zero when the register is written.
• Bit 5 – ICIE0: Timer/Counter0, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter0 Input Capture interrupt is enabled. The
corresponding Interrupt Vector (See “Interrupts” on page 66.) is executed when the
ICF0 Flag, located in TIFR0, is set.
• Bit 2 – OCIE0B: Timer/Counter0, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter0 Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector (see
TIFR0, is set.
• Bit 1 – OCIE0A: Timer/Counter0, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter0 Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector (see
TIFR0, is set.
• Bit 0 – TOIE0: Timer/Counter0, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter0 Overflow interrupt is enabled. The corresponding Interrupt Vector
(see
Bit
0x23
0x22
Read/Write
Initial Value
Bit
0x2B
Read/Write
Initial Value
“Interrupts” on page
“Accessing 16-bit Registers” on page
R/W
R
“Accessing 16-bit Registers” on page
7
0
7
–
0
“Interrupts” on page
“Interrupts” on page
R/W
36) is executed when the TOV0 flag, located in TIFR0, is set.
R
6
0
6
–
0
R/W
ICIE0
R/W
5
0
5
0
R/W
36) is executed when the OCF0B flag, located in
36) is executed when the OCF0A flag, located in
4
0
R
4
–
0
ICR0[15:8]
ICR0[7:0]
72.
R/W
3
0
R
3
–
0
72.
OCIE0B
R/W
R/W
2
0
2
0
ATtiny4/5/9/10
OCIE0A
R/W
R/W
1
0
1
0
R/W
TOIE0
R/W
0
0
0
0
ICR0H
TIMSK0
ICR0L
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