PIC16F57-I/P Microchip Technology, PIC16F57-I/P Datasheet - Page 44

IC MCU FLASH 2KX12 28DIP

PIC16F57-I/P

Manufacturer Part Number
PIC16F57-I/P
Description
IC MCU FLASH 2KX12 28DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets

Specifications of PIC16F57-I/P

Program Memory Type
FLASH
Program Memory Size
3KB (2K x 12)
Package / Case
28-DIP (0.600", 15.24mm)
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
POR, WDT
Number Of I /o
20
Ram Size
72 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
72 B
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
20
Number Of Timers
1
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
DV164120, DV164101, ICE2000
Minimum Operating Temperature
- 40 C
Data Rom Size
2 K
Height
3.3 mm
Length
34.67 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2 V
Width
7.24 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28XP - SOCKET TRANSITION ICE 28DIPAC164001 - MODULE SKT PROMATEII 18/28DIP
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Quantity
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Part Number:
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0
PIC16F5X
TABLE 9-2:
DS41213D-page 42
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
LITERAL AND CONTROL OPERATIONS
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
OPTION
RETLW
SLEEP
TRIS
XORLW
Note 1:
Mnemonic,
Operands
2:
3:
4:
The 9th bit of the program counter will be forced to a ‘0’ by any instruction that writes to the PC except for
GOTO (see Section 3.5 “Program Counter” for more on program counter).
When an I/O register is modified as a function of itself (e.g., MOVF PORTB, 1), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and
is driven low by an external device, the data will be written back with a ‘0’.
The instruction TRIS f, where f = 5, 6 or 7 causes the contents of the W register to be written to the
tri-state latches of PORTA, B or C, respectively. A ‘1’ forces the pin to a high-impedance state and
disables the output buffers.
If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be
cleared (if assigned to TMR0).
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, b
f, b
f, b
f, b
k
k
k
k
k
k
f
k
INSTRUCTION SET SUMMARY
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate left f through Carry
Rotate right f through Carry
Subtract W from f
Swap f
Exclusive OR W with f
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
AND literal with W
Subroutine Call
Clear Watchdog Timer
Unconditional branch
Inclusive OR Literal with W
Move Literal to W
Load OPTION register
Return, place Literal in W
Go into Standby mode
Load TRIS register
Exclusive OR Literal to W
Description
Cycles
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
2
1
1
1
2
1
1
1
(2)
(2)
(2)
(2)
0001
0001
0000
0000
0010
0000
0010
0010
0011
0001
0010
0000
0000
0011
0011
0000
0011
0001
0100
0101
0110
0111
1110
1001
0000
101k
1101
1100
0000
1000
0000
0000
1111
MSb
12-Bit Opcode
11df
01df
011f
0100
01df
11df
11df
10df
11df
00df
00df
001f
0000
01df
00df
10df
10df
10df
bbbf
bbbf
bbbf
bbbf
kkkk
kkkk
0000
kkkk
kkkk
kkkk
0000
kkkk
0000
0000
kkkk
© 2007 Microchip Technology Inc.
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
kkkk
kkkk
0100
kkkk
kkkk
kkkk
0010
kkkk
0011
0fff
kkkk
LSb
Affected
C,DC,Z
C,DC,Z
TO
TO
Status
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
C
C
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
,
,
PD
PD
Notes
1, 2, 4
1, 2, 4
2, 4
2, 4
2, 4
2, 4
2, 4
2, 4
2, 4
1, 4
2, 4
2, 4
2, 4
2, 4
2, 4
2,4
4
1
3

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