PIC16F688-E/ML Microchip Technology, PIC16F688-E/ML Datasheet - Page 365
PIC16F688-E/ML
Manufacturer Part Number
PIC16F688-E/ML
Description
IC PIC MCU FLASH 4KX14 16QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(204 pages)
3.PIC16F688T-ISL.pdf
(6 pages)
4.PIC16F688T-ISL.pdf
(4 pages)
5.PIC16F688T-ISL.pdf
(688 pages)
Specifications of PIC16F688-E/ML
Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Core Processor
PIC
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
12
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
16-QFN
Controller Family/series
PIC16F
No. Of I/o's
12
Eeprom Memory Size
256Byte
Ram Memory Size
256Byte
Cpu Speed
20MHz
No. Of Timers
2
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART, RS- 232, SCI, USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT16QFN1 - SOCKET TRANSITION 14DIP TO 16QFNAC162061 - HEADER INTRFC MPLAB ICD2 20PINAC162056 - HEADER INTERFACE ICD2 16F688
Lead Free Status / Rohs Status
Details
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F688T-ISL PDF datasheet #3
- PIC16F688T-ISL PDF datasheet #4
- PIC16F688T-ISL PDF datasheet #5
- Current page: 365 of 688
- Download datasheet (3Mb)
19.4
19.5
19.6
1997 Microchip Technology Inc.
Voltage Reference Accuracy/Error
Operation During Sleep
Effects of a Reset
The full range of V
sistors on the top and bottom of the resistor ladder network
approaching V
changes with fluctuations in V
in the Device Data Sheets electrical specification
When the device wakes up from sleep through an interrupt or a Watchdog Timer time-out, the
contents of the VRCON register are not affected. To minimize current consumption in SLEEP
mode, the Voltage Reference should be disabled.
A device reset disables the Voltage Reference by clearing the VREN bit (VRCON<7>). This reset
also disconnects the reference from the V
selects the high voltage range by clearing the VRR bit (VRCON<5>). The V
VRCON<3:0>, are also cleared.
SS
Section 19. Voltage Reference
or V
SS
to V
DD
. The Voltage Reference is V
DD
cannot be realized due to the construction of the module. The tran-
DD
. The absolute accuracy of the Voltage Reference can be found
REF
pin by clearing the VROE bit (VRCON<6>) and
parameter
DD
derived and therefore, the V
D311.
(Figure
19-1) keep V
REF
DS31019A-page 19-5
value select bits,
REF
REF
output
from
19
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