PIC24F04KA201T-I/MQ Microchip Technology, PIC24F04KA201T-I/MQ Datasheet - Page 47
PIC24F04KA201T-I/MQ
Manufacturer Part Number
PIC24F04KA201T-I/MQ
Description
IC PIC MCU FLASH 512KX4 20-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheets
1.PIC24F04KA201-ISS.pdf
(8 pages)
2.PIC24F04KA201-ISS.pdf
(48 pages)
3.PIC24F04KA201-ISS.pdf
(224 pages)
4.PIC24F04KA201-ISS.pdf
(26 pages)
Specifications of PIC24F04KA201T-I/MQ
Program Memory Type
FLASH
Program Memory Size
4KB (1.375K x 24)
Package / Case
20-QFN
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
18
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24F
Core
PIC
Data Bus Width
16 bit
Data Ram Size
512 B
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
18
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM240001
Minimum Operating Temperature
- 40 C
On-chip Adc
9-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC24F04KA201-ISS PDF datasheet
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REGISTER 5-1:
© 2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
-n = Value at POR
‘0’ = Bit is cleared
bit 15
bit 14
bit 13
bit 12
bit 11-7
bit 6
bit 5-0
Note 1:
R/SO-0, HC
WR
U-0
—
2:
3:
All other combinations of NVMOP<5:0> are no operation.
Available in ICSP™ mode only. Refer to device programming specification.
The address in the Table Pointer decides which rows will be erased.
WR: Write Control bit
1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is
0 = Program or erase operation is complete and inactive
WREN: Write Enable bit
1 = Enable Flash program/erase operations
0 = Inhibit Flash program/erase operations
WRERR: Write Sequence Error Flag bit
1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically
0 = The program or erase operation completed normally
PGMONLY: Program Only Enable bit
Unimplemented: Read as ‘0’
ERASE: Erase/Program Enable bit
1 = Perform the erase operation specified by NVMOP<5:0> on the next WR command
0 = Perform the program operation specified by NVMOP<5:0> on the next WR command
NVMOP<5:0>: Programming Operation Command Byte bits
Erase Operations (when ERASE bit is ‘1’):
1010xx = Erase entire boot block (including code-protected boot block)
1001xx = Erase entire memory (including boot block, configuration block, general block)
011010 = Program/erase 4 rows of Flash memory
011001 = Program/erase 2 rows of Flash memory
011000 = Program/erase 1 row of Flash memory
0101xx = Erase entire configuration block (except code protection bits)
0011xx = Erase entire general memory block programming operations
ERASE
WREN
R/W-0
R/W-0
cleared by hardware once the operation is complete
on any set attempt of the WR bit)
NVMCON: FLASH MEMORY CONTROL REGISTER
x = Bit is unknown
SO = Settable Only bit
‘1’ = Bit is set
NVMOP5
WRERR
R/W-0
R/W-0
(1)
NVMOP4
PGMONLY
R/W-0
R/W-0
Preliminary
(1)
PIC24F04KA201 FAMILY
HC = Hardware Clearable bit
R = Readable bit
U = Unimplemented bit, read as ‘0’
NVMOP3
R/W-0
U-0
—
(3)
(3)
(3)
(1)
NVMOP2
(1)
R/W-0
U-0
—
(1)
(2)
W = Writable bit
NVMOP1
R/W-0
U-0
—
(1)
DS39937B-page 45
(2)
NVMOP0
R/W-0
U-0
—
bit 8
bit 0
(1)
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