AT90PWM1-16SU Atmel, AT90PWM1-16SU Datasheet - Page 33
![MCU AVR 8K FLASH 16MHZ 24-SOIC](/photos/6/70/67046/453-24-soic_sml.jpg)
AT90PWM1-16SU
Manufacturer Part Number
AT90PWM1-16SU
Description
MCU AVR 8K FLASH 16MHZ 24-SOIC
Manufacturer
Atmel
Series
AVR® 90PWM Lightingr
Datasheet
1.AT90PWM1-16SU.pdf
(297 pages)
Specifications of AT90PWM1-16SU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
19
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
24-SOIC (7.5mm Width)
Processor Series
AT90PWMx
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SPI
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
19
Number Of Timers
2
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRFBKIT, ATAVRISP2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
For Use With
ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT90PWM1-16SU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- Current page: 33 of 297
- Download datasheet (4Mb)
7.6.2
4378C–AVR–09/08
PLL Control and Status Register – PLLCSR
Table 7-8.
1.
2.
3.
Figure 7-3.
• Bit 7..3 – Res: Reserved Bits
These bits are reserved bits in the AT90PWM1 and always read as zero.
• Bit 2 – PLLF: PLL Factor
The PLLF bit is used to select the division factor of the PLL.
If PLLF is set, the PLL output is 64Mhz.
If PLLF is clear, the PLL output is 32Mhz.
• Bit 1 – PLLE: PLL Enable
Bit
$29 ($29)
Read/Write
Initial Value
CKSEL
Ext Clk
0001
3..0
This value do not provide a proper restart ; do not use PD in this clock scheme
This value do not provide a proper restart ; do not use PD in this clock scheme
This value do not provide a proper restart ; do not use PD in this clock scheme
XTAL1
XTAL2
SUT1..0
Start-up Times when the PLL is selected as system clock
PCK Clocking System AT90PWM2/3
00
01
10
11
RC OSCILLATOR
OSCCAL
8 MHz
R
7
–
0
OSCILLATORS
Start-up Time from Power-down
R
6
–
0
CKSEL3..0
and Power-save
R
5
–
0
6 CK
6 CK
6 CK
DIVIDE
BY 8
(1)
(2)
(3)
R
4
–
0
PLLE
PLL
64x
R
3
–
0
Reserved
Detector
Lock
PLLF
DIVIDE
DIVIDE
R/W
PLLF
BY 2
BY 4
2
0
Additional Delay from Reset
PLLE
R/W
0/1
1
14CK + 64 ms
14CK + 4 ms
(V
AT90PWM1
CC
14CK
= 5.0V)
PLOCK
CLK
PLOCK
CK
R
0
0
PLL
SOURCE
PLLCSR
33
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