PIC12C672-10E/P Microchip Technology, PIC12C672-10E/P Datasheet - Page 278
PIC12C672-10E/P
Manufacturer Part Number
PIC12C672-10E/P
Description
IC MCU OTP 2KX14 A/D 8DIP
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12CE673-10P.pdf
(129 pages)
3.PIC12CE673-10P.pdf
(14 pages)
Specifications of PIC12C672-10E/P
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
8-DIP (0.300", 7.62mm)
Processor Series
PIC12C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
5
Number Of Timers
8
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
- 40 C
On-chip Adc
8
Data Rom Size
128 B
Height
3.3 mm
Length
9.27 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
3 V
Width
6.35 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
- Current page: 278 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
17.1
SPI is a trademark of Motorola Corporation.
I
DS31017A-page 17-2
2
C is a trademark of Philips Corporation.
Introduction
The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicat-
ing with other peripheral or microcontroller devices. These peripheral devices may be serial
EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module can operate
in one of two modes:
• Serial Peripheral Interface (SPI™)
• Inter-Integrated Circuit (I
Figure 17-1
the block diagrams for the two different I
Figure 17-1:
- Full Master Mode
- Slave mode (with general address call)
shows a block diagram for the SPI mode, while
SPI Mode Block Diagram
SDO
SCK
SDI
SS
2
C™)
Preliminary
Read
SS Control
SMP:CKE
Select
Edge
Enable
bit0
Select
2
Edge
C modes of operation.
SSPBUF reg
Data to TX/RX in SSPSR
TRIS bit
2
SSPM3:SSPM0
SSPSR reg
Clock Select
4
2
shift clock
Prescaler
Write
4, 16, 64
Figure
TMR2 output
data bus
Internal
2
1997 Microchip Technology Inc.
17-2, and
T
OSC
Figure 17-3
show
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