ATMEGA16A-AUR Atmel, ATMEGA16A-AUR Datasheet - Page 126
ATMEGA16A-AUR
Manufacturer Part Number
ATMEGA16A-AUR
Description
MCU AVR 16KB FLASH 16MHZ 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA16A-MU.pdf
(352 pages)
Specifications of ATMEGA16A-AUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA16A-AUR
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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17.8
126
Timer/Counter Timing Diagrams
ATmega16A
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2 Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR2 is set equal to BOTTOM, the out-
put will be continuously low and if set equal to MAX the output will be continuously high for non-
inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of Period 2 in
there is no Compare Match. The point of this transition is to guarantee symmetry around BOT-
TOM. There are two cases that will give transition without Compare Match:
The following figures show the Timer/Counter in Synchronous mode, and the timer clock (clk
is therefore shown as a clock enable signal. In Asynchronous mode, clk
the Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are
set.
count sequence close to the MAX value in all modes other than phase correct PWM mode.
Figure 17-8. Timer/Counter Timing Diagram, no Prescaling
Figure 17-9
• OCR2A changes its value from Max, like in
• The Timer starts counting from a value higher than the one in OCR2A, and for that reason
OCn pin value is the same as the result of a down-counting Compare Match. To ensure
symmetry around BOTTOM the OCn value at MAX must be correspond the the result of an
up-counting Compare Match.
misses the Compare Match and hence the OCn that would have happened on the way up.
Figure 17-8
TCNTn
(clk
TOVn
clk
clk
I/O
I/O
Tn
/1)
shows the same timing data, but with the prescaler enabled.
contains timing data for basic Timer/Counter operation. The figure shows the
MAX - 1
Figure 17-7
MAX
OCn has a transition from high to l ow even though
Figure
17-7. When the OCR2A value is MAX the
BOTTOM
I/O
should be replaced by
BOTTOM + 1
8154B–AVR–07/09
T2
)
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