PIC16C770-E/SS Microchip Technology, PIC16C770-E/SS Datasheet - Page 212
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PIC16C770-E/SS
Manufacturer Part Number
PIC16C770-E/SS
Description
IC MCU OTP 2KX14 A/D PWM 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16C770-ISO.pdf
(220 pages)
2.PIC16C770-ISO.pdf
(6 pages)
3.PIC16C770-ISO.pdf
(8 pages)
Specifications of PIC16C770-E/SS
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 6x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SSOP
For Use With
XLT20SS1-1 - SOCKET TRANSITION 20DIP 20SSOP309-1014 - ADAPTER 20-SSOP TO 20-DIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
PIC16C770E/SS
PIC16C717/770/771
I
I/O Ports .............................................................................. 25
I
I
I
I
I
I
ICEPIC In-Circuit Emulator ............................................... 142
ID Locations .............................................................. 117, 131
In-Circuit Serial Programming (ICSP) ....................... 117, 131
INDF.................................................................................... 13
INDF Register ............................................................... 11, 12
Indirect Addressing ............................................................. 23
Instruction Format ............................................................. 133
Instruction Set ................................................................... 133
DS41120B-page 210
2
2
2
2
2
2
C ....................................................................................... 76
C Master Mode Reception................................................ 89
C Master Mode Restart Condition .................................... 86
C Mode Selection ............................................................. 76
C Module
C Slave Mode ................................................................... 76
Acknowledge Sequence timing ................................... 91
Addressing .................................................................. 77
Baud Rate Generator .................................................. 84
Block Diagram............................................................. 83
BRG Block Diagram .................................................... 84
BRG Reset due to SDA Collision ................................ 96
BRG Timing ................................................................ 85
Bus Arbitration ............................................................ 94
Bus Collision ............................................................... 94
Bus Collision timing..................................................... 94
Clock Arbitration.......................................................... 93
Clock Arbitration Timing (Master Transmit)................. 93
Conditions to not give ACK Pulse ............................... 77
General Call Address Support .................................... 82
Master Mode ............................................................... 83
Master Mode 7-bit Reception timing ........................... 90
Master Mode Operation .............................................. 84
Master Mode Start Condition ...................................... 85
Master Mode Transmission......................................... 87
Master Mode Transmit Sequence ............................... 84
Multi-Master Communication ...................................... 94
Multi-master Mode ...................................................... 84
Operation .................................................................... 76
Repeat Start Condition timing ..................................... 86
Slave Mode ................................................................. 76
Slave Reception .......................................................... 78
Slave Transmission..................................................... 80
SSPBUF...................................................................... 76
Stop Condition Receive or Transmit timing................. 92
Stop Condition timing .................................................. 92
Waveforms for 7-bit Reception ................................... 78
Waveforms for 7-bit Transmission .............................. 80
FSR Register ................................................................ 9
ADDLW ..................................................................... 135
ADDWF ..................................................................... 135
ANDLW ..................................................................... 135
ANDWF ..................................................................... 135
BCF ........................................................................... 135
BSF ........................................................................... 135
BTFSC ...................................................................... 136
Acknowledge....................................................... 94
Restart Condition ................................................ 97
Restart Condition Timing (Case1)....................... 97
Restart Condition Timing (Case2)....................... 97
Start Condition .................................................... 95
Start Condition Timing .................................. 95, 96
Stop Condition .................................................... 98
Stop Condition Timing (Case1)........................... 98
Stop Condition Timing (Case2)........................... 98
Transmit Timing .................................................. 94
INT Interrupt (RB0/INT). See Interrupt Sources
INTCON .............................................................................. 13
INTCON Register................................................................ 16
Inter-Integrated Circuit (I
internal sampling switch (Rss) impedence ....................... 113
Interrupt Sources ...................................................... 117, 127
Interrupts
Interrupts, Context Saving During..................................... 128
Interrupts, Enable Bits
BTFSS ...................................................................... 136
CALL......................................................................... 136
CLRF ........................................................................ 136
CLRW ....................................................................... 136
CLRWDT .................................................................. 136
COMF ....................................................................... 137
DECF ........................................................................ 137
DECFSZ ................................................................... 137
GOTO ....................................................................... 137
INCF ......................................................................... 137
INCFSZ..................................................................... 137
IORLW ...................................................................... 138
IORWF...................................................................... 138
MOVF ....................................................................... 138
MOVLW .................................................................... 138
MOVWF .................................................................... 138
NOP .......................................................................... 138
RETFIE ..................................................................... 139
RETLW ..................................................................... 139
RETURN................................................................... 139
RLF ........................................................................... 139
RRF .......................................................................... 139
SLEEP ...................................................................... 139
SUBLW ..................................................................... 140
SUBWF..................................................................... 140
SWAPF ..................................................................... 140
XORLW .................................................................... 140
XORWF .................................................................... 140
Summary Table ........................................................ 134
GIE Bit ........................................................................ 16
INTE Bit ...................................................................... 16
INTF Bit ...................................................................... 16
PEIE Bit ...................................................................... 16
RBIE Bit ...................................................................... 16
RBIF Bit ................................................................ 16, 33
T0IE Bit ....................................................................... 16
T0IF Bit ....................................................................... 16
Block Diagram .......................................................... 127
Capture Complete (ECCP) ......................................... 54
Compare Complete (ECCP) ....................................... 55
RB0/INT Pin, External............................................... 128
TMR0 Overflow................................................... 46, 128
TMR1 Overflow..................................................... 47, 49
TMR2 to PR2 Match ................................................... 52
TMR2 to PR2 Match (PWM) ................................. 51, 56
Synchronous Serial Port Interrupt............................... 18
A/D Converter Enable (ADIE Bit)................................ 17
CCP1 Enable (CCP1IE Bit) .................................. 17, 54
Global Interrupt Enable (GIE Bit) ........................ 16, 127
Interrupt-on-Change (RB7:RB4) Enable
Peripheral Interrupt Enable (PEIE Bit) ........................ 16
PSP Read/Write Enable (PSPIE Bit) .......................... 17
RB0/INT Enable (INTE Bit) ......................................... 16
SSP Enable (SSPIE Bit) ............................................. 17
TMR0 Overflow Enable (T0IE Bit) .............................. 16
TMR1 Overflow Enable (TMR1IE Bit)......................... 17
(RBIE Bit)........................................................ 16, 128
2
C) ............................................... 65
2002 Microchip Technology Inc.