PIC16C770-E/SS Microchip Technology, PIC16C770-E/SS Datasheet - Page 71
![IC MCU OTP 2KX14 A/D PWM 20SSOP](/photos/6/58/65895/150-20-ssop_sml.jpg)
PIC16C770-E/SS
Manufacturer Part Number
PIC16C770-E/SS
Description
IC MCU OTP 2KX14 A/D PWM 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16C770-ISO.pdf
(220 pages)
2.PIC16C770-ISO.pdf
(6 pages)
3.PIC16C770-ISO.pdf
(8 pages)
Specifications of PIC16C770-E/SS
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 6x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SSOP
For Use With
XLT20SS1-1 - SOCKET TRANSITION 20DIP 20SSOP309-1014 - ADAPTER 20-SSOP TO 20-DIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
PIC16C770E/SS
- Current page: 71 of 220
- Download datasheet (4Mb)
REGISTER 9-3:
2002 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SYNC SERIAL PORT CONTROL REGISTER2 (SSPCON2: 91h)
GCEN: General Call Enable bit (In I
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR.
0 = General call address disabled.
ACKSTAT: Acknowledge Status bit (In I
In Master Transmit mode:
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
ACKDT: Acknowledge Data bit (In I
In Master Receive mode:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of
1 = Not Acknowledge (NACK)
0 = Acknowledge (ACK)
ACKEN: Acknowledge Sequence Enable bit (In I
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
0 = Acknowledge sequence IDLE
RCEN: Receive Enable bit (In I
1 = Enables Receive mode for I
0 = Receive IDLE
PEN: STOP Condition Enable bit (In I
SCK Release Control
1 = Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware.
0 = STOP condition IDLE
RSEN: Repeated START Condition Enabled bit (In I
1 = Initiate Repeated START condition on SDA and SCL pins. Automatically cleared by
0 = Repeated START condition IDLE
SEN: START Condition Enabled bit (In I
1 = Initiate START condition on SDA and SCL pins. Automatically cleared by hardware.
0 = START condition IDLE
bit 7
Legend:
R = Readable bit
- n = Value at POR
Note:
R/W-0
GCEN
a receive.
Automatically cleared by hardware.
hardware.
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I
mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or
writes to the SSPBUF are disabled).
ACKSTAT
R/W-0
Advance Information
ACKDT
R/W-0
W = Writable bit
’1’ = Bit is set
2
2
C Master mode only).
C
2
2
C Master mode only)
C Slave mode only)
ACKEN
2
R/W-0
C Master mode only).
2
2
C Master mode only)
C Master mode only)
PIC16C717/770/771
2
R/W-0
RCEN
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
C Master mode only).
2
C Master mode only)
R/W-0
PEN
2
C module is not in the IDLE
x = Bit is unknown
R/W-0
RSEN
DS41120B-page 69
R/W-0
SEN
bit 0
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