AT32UC3L016-ZAUT Atmel, AT32UC3L016-ZAUT Datasheet - Page 475
AT32UC3L016-ZAUT
Manufacturer Part Number
AT32UC3L016-ZAUT
Description
IC MCU AVR32 16KB FLASH 48VQFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3L-EK.pdf
(858 pages)
Specifications of AT32UC3L016-ZAUT
Core Processor
AVR
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, PWM, WDT
Number Of I /o
36
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SPI, TWI, USART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
36
Number Of Timers
7
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
AT32UC3L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 9 Channel
Length
7 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
1.62 V
Width
7 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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Figure 21-9. Master Read with Multiple Data Bytes
21.8.5
21.8.5.1
32099F–11/2010
SR.IDLE
RXRDY
TWD
Using the Peripheral DMA Controller
NBYTES set to m
Write START +
Data Transmit with the Peripheral DMA Controller
S
STOP bit
DADR
Programming CMDR with START=STOP=1 and NBYTES=0 will generate a transmission with
no data bytes, ie START, DADR+R, STOP
The TWI transfers require the master to acknowledge each received data byte. During the
acknowledge clock pulse (9th pulse), the slave releases the data line (HIGH), enabling the
master to pull it down in order to generate the acknowledge. All data bytes except the last are
acknowledged by the master. Not acknowledging the last byte informs the slave that the trans-
fer is finished.
RXRDY is used as Receive Ready for the Peripheral DMA Controller receive channel.
Figure 21-8. Master Read with One Data Byte
The use of the Peripheral DMA Controller significantly reduces the CPU load. The program-
mer can set up ring buffers for the DMA controller, containing data to transmit or free buffer
space to place received data.
To assure correct behavior, respect the following programming sequences:
1. Initialize the transmit Peripheral DMA Controller (memory pointers, size, etc.).
2. Configure the TWIM (ADR, NBYTES, etc.).
R
A
SR.IDLE
RXRDY
TWD
DATAn
NBYTES set to 1
Write START &
S
STOP bit
Read RHR
DADR
DATAn
A
DATAn+1
R
DATAn+m-2
Read RHR
A
DATAn+m-1
DATA
AT32UC3L016/32/64
DATAn+m-1
Read RHR
A
N
Read RHR
DATAn+m
When NBYTES=0
P
Send STOP
N
Read RHR
DATAn+m
P
475
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