ATXMEGA16A4-CUR Atmel, ATXMEGA16A4-CUR Datasheet - Page 144
ATXMEGA16A4-CUR
Manufacturer Part Number
ATXMEGA16A4-CUR
Description
MCU AVR 16+4KB FLASH 49VFBGA
Manufacturer
Atmel
Series
AVR® XMEGAr
Specifications of ATXMEGA16A4-CUR
Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
49-VFBGA
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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13.15.3
8077H–AVR–12/09
VPCTRLB - Virtual Port-map Control Register B
• Bit 7:4 - VP1MAP: Virtual Port 1 Mapping
These bits decide which ports should be mapped to Virtual Port 1. The registers DIR, OUT, IN
and INTFLAGS will be mapped. Accessing the virtual port registers is equal to accessing the
actual port registers. See
• Bit 3:0 - VP0MAP: Virtual Port 0 Mapping
These bits decide which ports should be mapped to Virtual Port 0. The registers DIR, OUT, IN
and INTFLAGS will be mapped. Accessing the virtual port registers is equal to accessing the
actual port registers. See
• Bit 7:4 - VP3MAP: Virtual Port 3 Mapping
These bits decide which ports should be mapped to Virtual Port 3. The registers DIR, OUT, IN
and INTFLAGS will be mapped. Accessing the virtual port registers is equal to accessing the
actual port registers. See
• Bit 3:0 - VP2MAP: Virtual Port 2 Mapping
These bits decide which ports should be mapped to Virtual Port 2. The registers DIR, OUT, IN
and INTFLAGS will be mapped. Accessing the virtual port registers is equal to accessing the
actual port registers. See
Table 13-6.
Bit
+0x03
Read/Write
Initial Value
VPnMAP[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
R/W
7
0
Virtual Port mapping.
Group Configuration
PORTA
PORTB
PORTC
PORTD
PORTE
PORTF
PORTG
PORTH
PORTJ
PORTK
PORTL
PORTM
PORTN
R/W
6
0
VP3MAP[3:0]
Table 13-6
Table 13-6
Table 13-6
Table 13-6
R/W
5
0
for configuration.
for configuration.
for configuration.
for configuration.
R/W
4
0
R/W
3
0
Description
PORTA mapped to virtual Port n
PORTB mapped to virtual Port n
PORTC mapped to virtual Port n
PORTD mapped to virtual Port n
PORTE mapped to virtual Port n
PORTF mapped to virtual Port n
PORTG mapped to virtual Port n
PORTH mapped to virtual Port n
PORTJ mapped to virtual Port n
PORTK mapped to virtual Port n
PORTL mapped to virtual Port n
PORTM mapped to virtual Port n
PORTN mapped to virtual Port n
R/W
2
0
VP2MAP[3:0]
R/W
1
0
XMEGA A
R/W
0
0
VPCTRLB
144
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