ATMEGA324PA-CU Atmel, ATMEGA324PA-CU Datasheet - Page 172
ATMEGA324PA-CU
Manufacturer Part Number
ATMEGA324PA-CU
Description
MCU AVR 32K FLASH 20MHZ BGA
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA324PA-CU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
49-VFBGA
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
2-Wire, JTAG, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATQT600
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Price
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18. USART
18.1
18.2
18.3
8272A–AVR–01/10
Features
USART1 and USART0
Overview
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The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P has two USART’s, USART0
and USART1.
The functionality for all USART’s is described below, most register and bit references in this sec-
tion are written in general form. A lower case “n” replaces the USART number.
USART0 and USART1 have different I/O registers as shown in
551.
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a
highly flexible serial communication device.
A simplified block diagram of the USART Transmitter is shown in
accessible I/O Registers and I/O pins are shown in bold.
The Power Reducion USART0 bit, PRUSART0, in
49
The Power Reducion USART1 bit, PRUSART1, in
49
164A/164PA/324A/324PA/644A/644PA/1284/1284P
Full Duplex Operation (Independent Serial Receive and Transmit Registers)
Asynchronous or Synchronous Operation
Master or Slave Clocked Synchronous Operation
High Resolution Baud Rate Generator
Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
Odd or Even Parity Generation and Parity Check Supported by Hardware
Data OverRun Detection
Framing Error Detection
Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
Multi-processor Communication Mode
Double Speed Asynchronous Communication Mode
must be disabled by writing a logical zero to it.
must be disabled by writing a logical zero to it.
”PRR – Power Reduction Register” on page
”PRR – Power Reduction Register” on page
Figure 18-1 on page
”Register Summary” on page
173. CPU
172
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