ATMEGA169P-16MU Atmel, ATMEGA169P-16MU Datasheet - Page 126
ATMEGA169P-16MU
Manufacturer Part Number
ATMEGA169P-16MU
Description
IC AVR MCU 16K 16MHZ IND 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA169PV-8AU.pdf
(395 pages)
Specifications of ATMEGA169P-16MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, USART, USI
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
54
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRBFLY
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
64MLF EP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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15.10 Timer/Counter Timing Diagrams
8018P–AVR–08/10
The extreme values for the OCR1x Register represents special cases when generating a PWM
waveform output in the phase and frequency correct PWM mode. If the OCR1x is set equal to
BOTTOM the output will be continuously low and if set equal to TOP the output will be set to
high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic val-
ues. If OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A
output will toggle with a 50% duty cycle.
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for
modes utilizing double buffering).
Figure 15-10. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling
Figure 15-11
Figure 15-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f
Figure 15-12 on page 127
using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM.
The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by
TCNTn
OCRnx
OCFnx
TCNTn
OCRnx
(clk
OCFnx
(clk
clk
clk
clk
clk
I/O
I/O
I/O
Tn
I/O
Tn
/1)
/8)
shows the same timing data, but with the prescaler enabled.
OCRnx - 1
OCRnx - 1
shows the count sequence close to TOP in various modes. When
Figure 15-10
OCRnx
OCRnx
OCRnx Value
OCRnx Value
shows a timing diagram for the setting of OCF1x.
OCRnx + 1
OCRnx + 1
T1
ATmega169P
) is therefore shown as a
OCRnx + 2
OCRnx + 2
clk_I/O
/8)
126
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