ATMEGA3250P-20AUR Atmel, ATMEGA3250P-20AUR Datasheet - Page 283
ATMEGA3250P-20AUR
Manufacturer Part Number
ATMEGA3250P-20AUR
Description
MCU AVR 32K FLASH 20MHZ 100TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA3250P-20AU.pdf
(364 pages)
Specifications of ATMEGA3250P-20AUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Manufacturer
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25.6.13
25.6.14
25.6.15
8023F–AVR–07/09
Reading the Signature Bytes
Reading the Calibration Byte
Parallel Programming Characteristics
Figure 25-6. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read
The algorithm for reading the Signature bytes is as follows (refer to
page 277
1. A: Load Command “0000 1000”.
2. B: Load Address Low Byte (0x00 - 0x02).
3. Set OE to “0”, and BS1 to “0”. The selected Signature byte can now be read at DATA.
4. Set OE to “1”.
The algorithm for reading the Calibration byte is as follows (refer to
page 277
1. A: Load Command “0000 1000”.
2. B: Load Address Low Byte, 0x00.
3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.
4. Set OE to “1”.
Figure 25-7. Parallel Programming Timing, Including some General Timing Requirements
(DATA, XA0/1, BS1, BS2)
for details on Command and Address loading):
for details on Command and Address loading):
Data & Contol
Extended Fuse Byte
Fuse Low Byte
RDY/BSY
Fuse High Byte
PAGEL
XTAL1
Lock Bits
WR
t
t
BVPH
DVXH
BS2
BS2
t
t
XHXL
PHPL
0
1
0
1
t
t
t
t
XLDX
XLWL
PLBX
PLWL
t
BVWL
ATmega325P/3250P
BS1
t
WLWH
WLRL
0
1
”Programming the Flash” on
”Programming the Flash” on
t
WLBX
DATA
t
WLRH
283
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