PIC18F8410-E/PT Microchip Technology, PIC18F8410-E/PT Datasheet - Page 12
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PIC18F8410-E/PT
Manufacturer Part Number
PIC18F8410-E/PT
Description
IC PIC MCU FLASH 16KX16 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F6310-IPT.pdf
(412 pages)
2.PIC18F6310-IPT.pdf
(16 pages)
3.PIC18F6310-IPT.pdf
(4 pages)
4.PIC18F6310-IPT.pdf
(28 pages)
5.PIC18F6310-IPT.pdf
(6 pages)
6.PIC18F6310-IPT.pdf
(4 pages)
Specifications of PIC18F8410-E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TFQFP
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F8410-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC18F6310/6410/8310/8410
32. Module: Timer1
33. Module: MSSP
34. Module: MSSP
DS80206F-page 12
In 16-Bit Asynchronous Counter mode (with or
without use of the Timer1 oscillator), the TMR1H
and TMR3H buffers do not update when TMRxL is
read.
This issue only affects reading the TMRxH regis-
ters. The timers increment and set the interrupt
flags as expected. The timer registers can also be
written as expected.
Work around
1. Use 8-bit mode by clearing the RD16 bit
2. Use the internal clock synchronization option
Date Codes that pertain to this issue:
All engineering and production devices.
The MSSP configured in SPI slave mode will gener-
ate a write collision if SSPBUF is updated and the
previous SSPBUF contents have not been
transferred
Reinitializing the MSSP by clearing and setting the
SSPEN (SSPCON1<5>) bit prior to rewriting
SSPBUF will not prevent the error condition.
Work around
Prior to updating the SSPBUF register with a new
value, verify whether the previous contents were
transferred by reading the BF (SSPSTAT<0>) bit. If
the previous byte has not been transferred, update
SSPBUF and clear the WCOL (SSPCON1<7>) bit if
necessary.
Date Codes that pertain to this issue:
All engineering and production devices.
In SPI mode, the SDO output may change after the
inactive clock edge of the bit ‘0’ output. This may
affect some SPI components that read data over
300 ns after the inactive edge of SCK.
Work around
None
Date Codes that pertain to this issue:
All engineering and production devices.
(T1CON<7>).
by clearing the T1SYNC bit (T1CON<2>).
to the shift register
.
35. Module: MSSP
36. Module: Reset
It has been observed that, following a Power-on
Reset, I
configuring the SCL and SDA pins as either inputs
or outputs. This has only been seen in a few
unique system environments.
A test of a statistically significant sample of
pre-production systems, across the voltage and
current range of the application’s power supply,
should indicate if a system is susceptible to this
issue.
Work around
Before configuring the module for I
1. Configure the SCL and SDA pins as outputs by
2. Force SCL and SDA low by clearing the
3. While keeping the LAT bits clear, configure
Once this is done, use the SSPCON1 and
SSPCON2 registers to configure the proper I
mode as before.
Date Codes that pertain to this issue:
All engineering and production devices.
This version of silicon does not support the func-
tionality described in Note 1 of parameter D002 in
Section 26.1 “DC Characteristics: Supply
Voltage” of the data sheet. The RAM content may
be altered during a Reset event if following
conditions are met.
• Device is accessing RAM.
• Asynchronous Reset (i.e., WDT, BOR or MCLR
Work around
None
Date Codes that pertain to this issue:
All engineering and production devices.
occurs when a write operation is being
executed (start of a Q4 cycle).
clearing their corresponding TRIS bits.
corresponding LAT bits.
SCL and SDA as inputs by setting their TRIS
bits.
2
C mode may not initialize properly by just
© 2007 Microchip Technology Inc.
2
C operation:
2
C