PIC18F4455-I/P Microchip Technology, PIC18F4455-I/P Datasheet - Page 215
PIC18F4455-I/P
Manufacturer Part Number
PIC18F4455-I/P
Description
IC PIC MCU FLASH 12KX16 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PCM18XR1.pdf
(438 pages)
3.PIC18F2221-ISO.pdf
(46 pages)
4.PIC18F2455-ISO.pdf
(14 pages)
5.PIC18F2455-ISO.pdf
(8 pages)
6.PIC18F2455-ISO.pdf
(26 pages)
7.PIC18F4550-IP.pdf
(430 pages)
8.PIC18LF2455-ISO.pdf
(430 pages)
Specifications of PIC18F4455-I/P
Program Memory Type
FLASH
Program Memory Size
24KB (12K x 16)
Package / Case
40-DIP (0.600", 15.24mm)
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
35
Eeprom Size
256 x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SPI/I2C/EAUSART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
35
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163025
Minimum Operating Temperature
- 40 C
On-chip Adc
13-ch x 10-bit
Package
40PDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
48 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3-DB18F4550 - BOARD DAUGHTER ICEPIC3DM163025 - PIC DEM FULL SPEED USB DEMO BRDDVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LD444-1001 - DEMO BOARD FOR PICMICRO MCUACICE0206 - ADAPTER MPLABICE 40P 600 MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F4455-I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Company:
Part Number:
PIC18F4455-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F4455-I/PT
Manufacturer:
MICROCH
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PCM18XR1 PDF datasheet #2
- PIC18F2221-ISO PDF datasheet #3
- PIC18F2455-ISO PDF datasheet #4
- PIC18F2455-ISO PDF datasheet #5
- PIC18F2455-ISO PDF datasheet #6
- PIC18F4550-IP PDF datasheet #7
- PIC18LF2455-ISO PDF datasheet #8
- Current page: 215 of 438
- Download datasheet (7Mb)
19.4.3.2
Masking an address bit causes that bit to become a
“don’t care”. When one address bit is masked, two
addresses will be Acknowledged and cause an
interrupt. It is possible to mask more than one address
bit at a time, which makes it possible to Acknowledge
up to 31 addresses in 7-bit mode and up to
63 addresses in 10-bit mode (see Example 19-3).
The I
masking is used or not. However, when address
masking is used, the I
multiple addresses and cause interrupts. When this
occurs, it is necessary to determine which address
caused the interrupt by checking SSPBUF.
In
ADMSK<5:1> (SSPCON2<5:1>) mask the corre-
sponding address bits in the SSPADD register. For any
ADMSK bits that are set (ADMSK<n> = 1), the
corresponding
(SSPADD<n> = x). For the module to issue an address
Acknowledge, it is sufficient to match only on
addresses that do not have an active address mask.
EXAMPLE 19-3:
© 2009 Microchip Technology Inc.
7-bit addressing:
10-bit addressing:
7-Bit
2
C Slave behaves the same way whether address
SSPADD<7:1> = A0h (1010000) (SSPADD<0> is assumed to be ‘0’)
ADMSK<5:1>
Addresses Acknowledged : A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh
SSPADD<7:0> = A0h (10100000) (The two MSbs of the address are ignored in this example, since
they are not affected by masking)
ADMSK<5:1>
Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh,
AEh, AFh
Address
Address Masking
address
ADDRESS MASKING EXAMPLES
mode,
= 00111
= 00111
2
C slave can Acknowledge
address
bit
is
mask
PIC18F2455/2550/4455/4550
ignored
bits
In 10-Bit Address mode, bits ADMSK<5:2> mask the
corresponding address bits in the SSPADD register. In
addition, ADMSK1 simultaneously masks the two LSbs
of the address (SSPADD<1:0>). For any ADMSK bits
that are active (ADMSK<n> = 1), the corresponding
address bit is ignored (SSPADD<n> = x). Also note
that although in 10-Bit Addressing mode, the upper
address bits reuse part of the SSPADD register bits, the
address mask bits do not interact with those bits. They
only affect the lower address bits.
Note 1: ADMSK1 masks the two Least Significant
2: The two Most Significant bits of the
bits of the address.
address are not affected by address
masking.
DS39632E-page 213
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