AT89C51RE2-RLTUM Atmel, AT89C51RE2-RLTUM Datasheet - Page 159

• Manufacturer Part Number: AT89C51RE2-RLTUM
• Description: MCU 8051 128K FLASH 44-VQFP
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51RE2-RLTUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 60MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: UART, SPI
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89OCD-01
• Minimum Operating Temperature: - 40 C
• Height: 1.45 mm
• Length: 10.1 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 10.1 mm
• For Use With: AT89STK-11 - KIT STARTER FOR AT89C51RX2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Serial Peripheral DATa
Register (SPDAT)
7663E–8051–10/08
Reset Value = 00X0 XXXXb
Not Bit addressable
The Serial Peripheral Data Register (Table 117) is a read/write buffer for the receive data regis-
ter. A write to SPDAT places data directly into the shift register. No transmit buffer is available in
this model.
A Read of the SPDAT returns the value located in the receive buffer and not the content of the
shift register.
Table 117. SPDAT Register
SPDAT - Serial Peripheral Data Register (C5H)
Reset Value = Indeterminate
R7:R0: Receive data bits
Bit Number
R7
7
4
3
2
1
0
Mnemonic
MODFIE
UARTM
SPTEIE
MODF
SPTE
Bit
R6
6
Description
Mode Fault
- Set by hardware to indicate that the SS pin is in inappropriate logic level (in both master
and slave modes).
- Cleared by hardware when reading SPSCR
When MODF error occurred:
- In slave mode: SPI interface ignores all transmitted data while SS remains high. A new
transmission is perform as soon as SS returns low.
- In master mode: SPI interface is disabled (SPEN=0, see description for SPEN bit in
SPCON register).
Serial Peripheral Transmit register Empty
- Set by hardware when transmit register is empty (if needed, SPDAT can be loaded with
another data).
- Cleared by hardware when transmit register is full (no more data should be loaded in
SPDAT).
Serial Peripheral UART mode
Set and cleared by software:
- Clear: Normal mode, data are transmitted MSB first (default)
- Set: UART mode, data are transmitted LSB first.
Interrupt Enable for SPTE
Set and cleared by software:
- Set to enable SPTE interrupt generation (when SPTE goes high, an interrupt is
generated).
- Clear to disable SPTE interrupt generation
Caution: When SPTEIE is set no interrupt generation occurred when SPIF flag goes high.
To enable SPIF interrupt again, SPTEIE should be cleared.
Interrupt Enable for MODF
Set and cleared by software:
- Set to enable MODF interrupt generation
- Clear to disable MODF interrupt generation
R5
5
R4
4
R3
3
R2
2
AT89C51RE2
R1
1
R0
0
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