DSPIC30F5015-30I/PT Microchip Technology, DSPIC30F5015-30I/PT Datasheet
DSPIC30F5015-30I/PT
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... Microchip Technology Inc. dsPIC30F5015/5016 Data Sheet High-Performance, 16-bit Digital Signal Controllers DS70149D ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... All DSP instructions single cycle • ±16-bit single-cycle shift © 2008 Microchip Technology Inc. dsPIC30F5015/5016 Peripheral Features: • High-current sink/source I/O pins: 25 mA/25 mA • Timer module with programmable prescaler: - Five 16-bit timers/counters; optionally pair 16-bit timers into 32-bit timer modules • ...
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... Selectable Power Management modes: - Sleep, Idle and Alternate Clock modes dsPIC30F Motor Control and Power Conversion Family Program SRAM Device Pins Mem. Bytes/ Bytes Instructions dsPIC30F5015 64 66K/22K 2048 dsPIC30F5016 80 66K/22K 2048 DS70149D-page 4 CMOS Technology: • Low-power, high-speed Flash technology • ...
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... PWM4H/RE7 4 T2CK/RC1 T4CK/RC3 5 SCK2/CN8/RG6 6 SDI2/CN9/RG7 7 SDO2/CN10/RG8 8 MCLR 9 SS2/CN11/RG9 FLTA/INT1/RE8 13 FLTB/INT2/RE9 14 AN5/QEB/CN7/RB5 15 AN4/QEA/CN6/RB4 16 AN3/INDX/CN5/RB3 17 AN2/SS1/CN4/RB2 18 PGC/EMUC/AN1/CN3/RB1 19 PGD/EMUD/AN0/CN2/RB0 20 . © 2008 Microchip Technology Inc. dsPIC30F5015/5016 dsPIC30F5016 EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/CN1/RC13 EMUC2/OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT3/RA14 V SS OSC2/CLKO/RC15 OSC1/CLKI V DD SCL/RG2 SDA/RG3 EMUC3/SCK1/INT0/RF6 SDI1/RF7 ...
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... PWM4L/RE6 2 PWM4H/RE7 3 SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/CN11/RG9 AN5/QEB/CN7/RB5 11 AN4/QEA/CN6/RB4 12 AN3/INDX/CN5/RB3 13 AN2/SS1/CN4/RB2 14 AN1/V -/CN3/RB1 15 REF AN0/V +/CN2/RB0 16 REF DS70149D-page 6 48 EMUC1/SOSCO/T1CK/CN0/RC14 47 EMUD1/SOSCI/T4CK/CN1/RC13 46 EMUC2/OC1/RD0 45 IC4/INT4/RD11 44 IC3/INT3/RD10 43 IC2/FLTB/INT2/RD9 42 IC1/FLTA/INT1/RD8 41 V dsPIC30F5015 SS 40 OSC2/CLKO/RC15 39 OSC1/CLKI SCL/RG2 36 SDA/RG3 35 EMUC3/SCK1/INT0/RF6 34 U1RX/SDI1/RF2 33 EMUD3/U1TX/SDO1/RF3 © 2008 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 DS70149D-page 7 ...
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... NOTES: DS70149D-page 8 © 2008 Microchip Technology Inc. ...
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... DSTEMP. Figure 1 block diagram of the DSTEMP device. Following the block diagram, Table 1-2 provides a brief description of the device I/O pinout and the functions that are multiplexed to the port pins on the DSTEMP. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 DS70149D-page 9 ...
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... FIGURE 1-1: dsPIC30F5015 BLOCK DIAGRAM Y Data Bus Interrupt PSV & Table Controller Data Access 8 24 Control Block 24 24 PCH PCU Program Counter Stack Address Latch Control Control Logic Logic Program Memory (66 Kbytes) Data EEPROM (1 Kbyte) 16 Data Latch ROM Latch 24 IR ...
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... DSTEMP device. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin. TABLE 1-1: I/O PIN DESCRIPTIONS FOR dsPIC30F5015 Pin Buffer Pin Name Type ...
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... TABLE 1-1: I/O PIN DESCRIPTIONS FOR dsPIC30F5015 (CONTINUED) Pin Buffer Pin Name Type Type MCLR I/P ST OCFA I ST OC1-OC4 O — OSC1 I ST/CMOS OSC2 I/O — PGD I/O ST PGC I ST RB0-RB15 I/O ST RC13-RC15 I/O ST RD0-RD11 I/O ST RE0-RE7 I/O ST RF0-RF6 I/O ST RG2-RG3 ...
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... POR/BOR Reset Watchdog MCLR Timer Low-Voltage Detect Input Capture CAN1 10-bit ADC Module SPI1, QEI Timers SPI2 © 2008 Microchip Technology Inc. dsPIC30F5015/5016 X Data Bus Data Latch Data Latch Y Data X Data 16 RAM RAM (1 Kbyte) (1 Kbyte) Address Address Latch Latch RAGU Y AGU ...
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... Table 1-1 provides a brief description of the device I/O pinout and the functions that are multiplexed to the port pins on the DSTEMP. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an over- ride of the data direction of the port pin. ...
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... ST = Schmitt Trigger input with CMOS levels I = Input © 2008 Microchip Technology Inc. dsPIC30F5015/5016 Description Master Clear (Reset) input or programming voltage input. This pin is an active- low Reset to the device. Compare Fault A input (for Compare channels and 4). Compare Fault B input (for Compare channels and 8). ...
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... NOTES: DS70149D-page 16 © 2008 Microchip Technology Inc. ...
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... For more information on the device instruction set and programming, refer to the “dsPIC30F/33F Programmer’s Reference Manual” (DS70157). This document provides a summary dsPIC30F5015/5016 CPU and peripheral function. For a complete description of this functionality, please refer to the “dsPIC30F Family Reference (DS70046). 2.1 Core Overview The core has a 24-bit instruction word ...
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... The core does not support a multi-stage instruction pipeline. However, a single stage instruction prefetch mechanism is used, which accesses and partially decodes instructions a cycle ahead of execution, in order to maximize available execution time. Most instructions execute in a single cycle, with certain exceptions. The core features a vectored exception processing structure for traps and interrupts, with 62 independent vectors ...
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... FIGURE 2-1: dsPIC30F5015/5016 PROGRAMMER’S MODEL DSP Operand Registers DSP Address Registers AD39 DSP ACCA Accumulators ACCB PC22 0 7 TABPAG TBLPAG Data Table Page Address 7 0 PSVPAG PSVPAG OAB SAB DA SRH © 2008 Microchip Technology Inc. dsPIC30F5015/5016 D15 D0 W0/WREG W10 W11 ...
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... Divide Support The dsPIC DSC devices feature a 16/16-bit signed fractional divide operation, as well as 32/16-bit and 16/16-bit signed and unsigned operations, in the form of single instruction iterative divides. The following instructions and data sizes are supported: 1. DIVF – 16/16 signed fractional divide 2. DIV.sd – ...
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... FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In © 2008 Microchip Technology Inc. dsPIC30F5015/5016 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Round u Logic Zero Backfill DS70149D-page 21 ...
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... MULTIPLIER The 17x17-bit multiplier is capable of signed or unsigned operations and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value ...
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... If the COVTE bit in the INTCON1 register is set, a catastrophic overflow can initiate a trap exception. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 2.4.2.2 Accumulator ‘Write Back’ The MAC class of instructions (with the exception of MPY, MPY.N, ED and EDAC) can optionally write a ...
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... Data Space Write Saturation In addition to adder/subtracter saturation, writes to data space may also be saturated, but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder ...
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... Device ID, the User ID and the Configuration bits. Otherwise, bit 23 is always clear. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 FIGURE 3-1: PROGRAM SPACE MEMORY MAP FOR dsPIC30F5015/5016 Reset - GOTO Instruction Reset - Target Address Interrupt Vector Table Reserved Alternate Vector Table User Flash ...
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... TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION Access Access Type Space Instruction Access User User TBLRD/TBLWT (TBLPAG<7> Configuration TBLRD/TBLWT (TBLPAG<7> Program Space Visibility User FIGURE 3-2: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Using Program 0 Counter Using 0 PSVPAG Reg Program Space ...
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... Program Memory ‘Phantom’ Byte (Read as ‘0’). © 2008 Microchip Technology Inc. dsPIC30F5015/5016 A set of table instructions are provided to move byte or word-sized data to and from program space. 1. TBLRDL: Table Read Low Word: Read the least significant word of the program address; ...
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... FIGURE 3-4: PROGRAM DATA TABLE ACCESS (MSB) PC Address 0x000000 00000000 0x000002 00000000 00000000 0x000004 0x000006 00000000 Program Memory ‘Phantom’ Byte (Read as ‘0’) 3.1.2 DATA ACCESS FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word program space page ...
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... The data space memory is split into two blocks, X and Y data space. A key element of this architecture is that Y space is a subset of X space, and is fully contained within X space. In order to provide an apparent linear addressing space, X and Y spaces have contiguous addresses. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 0x0000 (1) PSVPAG 0x00 8 0x8000 ...
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... FIGURE 3-6: dsPIC30F5015/5016 DATA SPACE MEMORY MAP MSB Address 0x0001 2 Kbyte SFR Space 0x07FF 0x0801 2 Kbyte 0x0BFF 0x0C01 SRAM Space 0x0FFF 0x1001 0x1FFF 0x8001 Optionally Mapped into Program Memory 0xFFFF DS70149D-page 30 16 bits MSB LSB SFR Space X Data RAM (X) Y Data RAM (Y) Unimplemented ≈ ...
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... DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE (Y SPACE) Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA using any W © 2008 Microchip Technology Inc. dsPIC30F5015/5016 SFR SPACE UNUSED Y SPACE UNUSED UNUSED MAC Class Ops Read-Only Indirect EA using W10, W11 ...
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... DATA SPACES The X data space is used by all instructions and supports all addressing modes. There are separate read and write data buses. The X read data bus is the return data path for all instructions that view data space as combined X and Y address space also the X address space data path for the dual operand read instructions (MAC class) ...
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... A PC push during exception processing will concatenate the SRL register to the MSB of the PC prior to the push. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 There is a Stack Pointer Limit register (SPLIM) associ- ated with the Stack Pointer. SPLIM is uninitialized at Reset the case for the Stack Pointer, SPLIM<0> ...
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TABLE 3-3: CORE REGISTER MAP Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) W0 0000 W1 0002 W2 0004 W3 0006 W4 0008 W5 000A W6 000C W7 000E W8 0010 W9 0012 W10 0014 ...
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TABLE 3-3: CORE REGISTER MAP (CONTINUED) Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) MODCON 0046 XMODEN YMODEN — XMODSRT 0048 XMODEND 004A YMODSRT 004C YMODEND 004E XBREV 0050 BREN DISICNT 0052 — — Legend: ...
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... NOTES: DS70149D-page 36 © 2008 Microchip Technology Inc. ...
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... Register Indirect Pre-Modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset © 2008 Microchip Technology Inc. dsPIC30F5015/5016 4.1.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space) ...
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... MOVE AND ACCUMULATOR INSTRUCTIONS Move instructions and the DSP Accumulator class of instructions provide a greater degree of addressing flexibility than other instructions. In addition to the addressing modes supported by instructions, Move and Accumulator instructions also support Register Indirect with Register Addressing mode, also referred to as Register Indexed mode ...
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... Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2008 Microchip Technology Inc. dsPIC30F5015/5016 4.2.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control register, MODCON<15:0>, contains enable flags, as well register field to specify the W Address registers. The XWM and YWM fields select which registers will operate with Modulo Addressing ...
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... MODULO ADDRESSING APPLICABILITY Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W register important to realize that the address boundaries check for addresses less than or greater than the upper (for incrementing buffers) and lower (for decrementing buffers) boundary addresses (not just equal to). Address changes may, therefore, jump beyond boundaries and still be adjusted correctly ...
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... TABLE 4-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) 4096 2048 1024 512 256 128 © 2008 Microchip Technology Inc. dsPIC30F5015/5016 Bit-Reversed Address Decimal XB<14:0> Bit-Reversed Address Modifier Value A0 Decimal ...
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... NOTES: DS70149D-page 42 © 2008 Microchip Technology Inc. ...
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... For more information on the device instruction set and programming, refer to the “dsPIC30F/33F Programmer’s Reference Manual” (DS70157). The dsPIC30F5015/5016 has 36 interrupt sources and 4 processor exceptions (traps), which must be arbitrated based on a priority scheme. The CPU is responsible for reading the Interrupt ...
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... Interrupt Priority The user-assignable Interrupt Priority (IP<2:0>) bits for each individual interrupt source are located in the Least Significant 3 bits of each nibble within the IPCx register(s). Bit 3 of each nibble is not used and is read as a ‘0’. These bits define the priority level assigned to a particular interrupt by the user ...
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... Trap Lockout: Occurrence of multiple trap conditions simultaneously will cause a Reset. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 5.3 Traps Traps can be considered as non-maskable interrupts indicating a software or hardware error, which adhere to a predefined priority, as shown in Figure 5-1. They ...
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... Address Error Trap: This trap is initiated when any of the following circumstances occurs: • A misaligned data word access is attempted. • A data fetch from unimplemented data memory location is attempted. • A data access of an unimplemented program memory location is attempted. • An instruction fetch from vector space is attempted ...
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... The RETFIE (Return from Interrupt) instruction will unstack the program counter and STATUS registers to return the processor to its state prior to the interrupt sequence. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 5.5 Alternate Vector Table In program memory, the Interrupt Vector Table (IVT) is followed by the Alternate Interrupt Vector Table (AIVT), as shown in Figure 5-1 ...
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... TABLE 5-2: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC30F5015 SFR ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name INTCON1 0080 NSTDIS — — — — INTCON2 0082 ALTIVT DISI — — — IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF IFS1 0086 — — ...
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TABLE 5-3: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC30F5016 SFR ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name INTCON1 0080 NSTDIS — — — — INTCON2 0082 ALTIVT — — — — IFS0 0084 CNIF MI2CIF SI2CIF ...
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... NOTES: DS70149D-page 50 © 2008 Microchip Technology Inc. ...
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... Using Table Instruction User/Configuration Space Select © 2008 Microchip Technology Inc. dsPIC30F5015/5016 manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. 6.2 Run-Time Self-Programming ...
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... RTSP Operation The dsPIC30F Flash program memory is organized into rows and panels. Each row consists of 32 instructions bytes. Each panel consists of 128 rows instructions. RTSP allows the user to erase one row (32 instructions time and to program 32 instructions at one time. Each panel of program memory contains write latches that hold 32 instructions of programming data ...
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... MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP © 2008 Microchip Technology Inc. dsPIC30F5015/5016 4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches. 5. Program 32 instruction words into program Flash. a) Set up NVMCON register for multi-word, program Flash, program, and set WREN bit ...
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... LOADING WRITE LATCHES Example 6-2 shows a sequence of instructions that can be used to load the 96 bytes of write latches. 32 TBLWTL and 32 TBLWTH instructions are needed to load the write latches selected by the Table Pointer. EXAMPLE 6-2: LOADING WRITE LATCHES ; Set up a pointer to the first program memory location to be written ...
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TABLE 6-1: NVM REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 NVMCON 0760 WR WREN WRERR NVMADR 0762 NVMADRU 0764 — — — NVMKEY 0766 — — — ...
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... NOTES: DS70149D-page 56 © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F5015/5016 A program or erase operation on the data EEPROM does not stop the instruction flow. The user is respon- sible for waiting for the appropriate duration of time before initiating another data EEPROM write/erase operation ...
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... Erasing Data EEPROM 7.2.1 ERASING A BLOCK OF DATA EEPROM In order to erase a block of data EEPROM, the NVMADRU and NVMADR registers must initially point to the block of memory to be erased. Configure NVMCON for erasing a block of data EEPROM, and set the ERASE and WREN bits in the NVMCON register ...
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... Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete © 2008 Microchip Technology Inc. dsPIC30F5015/5016 The write will not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word ...
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... WRITING A BLOCK OF DATA EEPROM To write a block of data EEPROM, write to all sixteen latches first, then set the NVMCON register and program the block. EXAMPLE 7-5: DATA EEPROM BLOCK WRITE MOV #LOW_ADDR_WORD,W0 MOV #HIGH_ADDR_WORD,W1 MOV W1 TBLPAG , MOV #data1,W2 [ W0]++ TBLWTL W2 , MOV #data2,W2 ...
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... WR Port Read LAT Read Port © 2008 Microchip Technology Inc. dsPIC30F5015/5016 Writes to the latch, write the latch (LATx). Reads from the port (PORTx), read the port pins and writes to the port pins, write the latch (LATx). Any bit and its associated data and control registers that are not valid for a particular device will be disabled ...
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... FIGURE 8-2: BLOCK DIAGRAM OF A SHARED PORT STRUCTURE Peripheral Module Peripheral Input Data Peripheral Module Enable Peripheral Output Enable Peripheral Output Data PIO Module Read TRIS Data Bus WR TRIS TRIS Latch WR LAT + WR Port Data Latch Read LAT Read Port 8.2 ...
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... TABLE 8-1: dsPIC30F5015 PORT REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISA 02C0 — — — — PORTA 02C2 — — — — LATA 02C4 — — — — TRISB 02C6 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 ...
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TABLE 8-2: dsPIC30F5016 PORT REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISA 02C0 TRISA15 TRISA14 — — PORTA 02C2 RA15 RA14 — — LATA 02C4 LATA15 LATA14 — — TRISB 02C6 TRISB15 TRISB14 TRISB13 ...
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... The input change notification module provides the dsPIC30F devices the ability to generate interrupt requests to the processor in response to a change-of-state on selected input pins. This module is capable of detecting input change-of-states, even in TABLE 8-3: INPUT CHANGE NOTIFICATION REGISTER MAP (BITS 15-8) FOR dsPIC30F5015 SFR Addr. Bit 15 Bit 14 Name ...
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... NOTES: DS70149D-page 66 © 2008 Microchip Technology Inc. ...
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... Interrupt on 16-bit Period register match or falling edge of external gate signal © 2008 Microchip Technology Inc. dsPIC30F5015/5016 These operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1 presents a block diagram of the 16-bit timer module. 16-bit Timer Mode: In the 16-bit Timer mode, the timer ...
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... FIGURE 9-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM (TYPE A TIMER) Equal Reset 0 T1IF Event Flag 1 TGATE SOSCO/ T1CK LPOSCEN SOSCI 9.1 Timer Gate Operation The 16-bit timer can be placed in the Gated Time Accumulation mode. This mode allows the internal T to increment the respective timer when the gate input signal (T1CK pin) is asserted high. Control bit TGATE (T1CON< ...
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... XTAL SOSCO pF 100K © 2008 Microchip Technology Inc. dsPIC30F5015/5016 9.5.1 RTC OSCILLATOR OPERATION When the TON = 1, TCS = 1 and TGATE = 0, the timer increments on the rising edge of the 32 kHz LP oscillator output signal the value specified in the Period register, and is then reset to ‘0’. ...
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TABLE 9-1: TIMER1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — Legend uninitialized bit; — = unimplemented bit, read as ‘0’ Note ...
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... Interrupt on a 32-bit Period register Match These operating modes are determined by setting the appropriate bit(s) in the 16-bit T2CON and T3CON SFRs. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 For 32-bit timer/counter operation, Timer2 is the least significant word and Timer3 is the most significant word of the 32-bit timer. Note: For 32-bit timer operation, T3CON control bits are ignored ...
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... FIGURE 10-1: 32-BIT TIMER2/3 BLOCK DIAGRAM Data Bus<15:0> TMR3HLD 16 Write TMR2 Read TMR2 16 Reset TMR3 MSB ADC Event Trigger Comparator x 32 Equal PR3 0 T3IF Event Flag 1 TGATE (T2CON<6>) T2CK Note: Timer Configuration bit T32, (T2CON<3>), must be set to ‘1’ for a 32-bit timer/counter operation. All control bits are respective to the T2CON register ...
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... TIMER2 BLOCK DIAGRAM (TYPE B TIMER) Equal Comparator x 16 Reset 0 T2IF Event Flag 1 TGATE (1) T2CK Note 1: T2CK input is not available on dsPIC30F5015. This input is grounded as shown in Figure 10-3. FIGURE 10-3: 16-BIT TIMER3 BLOCK DIAGRAM (TYPE C TIMER) ADC Event Trigger Equal Comparator x 16 Reset 0 T3IF Event Flag 1 ...
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... Timer Gate Operation The 32-bit timer can be placed in the Gated Time Accumulation mode. This mode allows the internal T to increment the respective timer when the gate input signal (T2CK pin) is asserted high. Control bit TGATE (T2CON<6>) must be set to enable this mode. When in this mode, Timer2 is the originating clock source ...
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... TSIDL — Legend uninitialized bit; — = unimplemented bit, read as ‘0’ Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. 2: This bit is not available in dsPIC30F5015 devices. (1) Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Timer2 Register Timer3 Holding Register (For 32-bit timer operations only) ...
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... NOTES: DS70149D-page 76 © 2008 Microchip Technology Inc. ...
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... T4CK Note: Timer Configuration bit T45, (T4CON<3>), must be set to ‘ control bits are respective to the T4CON register. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 The Timer4/5 module is similar in operation to the Timer2/3 module. differences, which are listed below: • The Timer4/5 module does not support the ADC Event Trigger feature • ...
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... TIMER5 BLOCK DIAGRAM (TYPE C TIMER) Equal ADC Event Trigger Reset 0 T5IF Event Flag 1 TGATE Note: The dsPIC30F5015/5016 devices do not have an external pin input to Timer5. In these devices, the following modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (gated time accumulation) DS70149D-page 78 PR4 TMR4 Q D TGATE ...
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TABLE 11-1: TIMER4/5 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR4 0114 TMR5HLD 0116 TMR5 0118 PR4 011A PR5 011C T4CON 011E TON — TSIDL — T5CON 0120 TON — TSIDL — Legend: u ...
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... NOTES: DS70149D-page 80 © 2008 Microchip Technology Inc. ...
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... N. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 These operating modes are determined by setting the appropriate bits (where x = 1,2,...,N). The dsPIC30F5015/5016 device has 8 capture channels. 12.1 Simple Capture Event Mode The simple capture events in the dsPIC30F product family are: • Capture every falling edge • ...
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... CAPTURE BUFFER OPERATION Each capture channel has an associated FIFO buffer, which is four 16-bit words deep. There are two status flags, which provide status on the FIFO buffer: • ICBFNE – Input Capture Buffer Not Empty • ICOV – Input Capture Overflow ...
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TABLE 12-1: INPUT CAPTURE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 IC1BUF 0140 IC1CON 0142 — — ICSIDL — IC2BUF 0144 IC2CON 0146 — — ICSIDL — IC3BUF 0148 IC3CON 014A — — ICSIDL ...
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... NOTES: DS70149D-page 84 © 2008 Microchip Technology Inc. ...
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... Compare registers. In the Dual Compare mode, the OCxR register is used for the first compare and OCxRS Set Flag bit OCxIF Output Logic 3 OCM<2:0> Mode Select OCTSEL T3P3_MATCH T2P2_MATCH in the 16-bit OCxCON SFR The dsPIC30F5015/5016 S Q OCx R Output Enable OCFA (for DS70149D-page 85 ...
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... Timer2 and Timer3 Selection Mode Each output compare channel can select between one of two 16-bit timers; Timer2 or Timer3. The selection of the timers is controlled by the OCTSEL bit (OCxCON<3>). Timer2 is the default timer resource for the output compare module. 13.2 Simple Output Compare Match Mode When control bits OCM< ...
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... Timer3) is enabled and the TSIDL bit of the selected timer is set to logic ‘0’. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 When the selected TMRx is equal to its respective Period register, PRx, the following four events occur on the next increment cycle: • ...
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TABLE 13-1: OUTPUT COMPARE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 OC1RS 0180 OC1R 0182 OC1CON 0184 — — OCSIDL — OC2RS 0186 OC2R 0188 OC2CON 018A — — OCSIDL — OC3RS ...
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... Existing Pin Logic 0 UPDN Up/Down 1 © 2008 Microchip Technology Inc. dsPIC30F5015/5016 The operational features of the QEI include: • Three input channels for two phase signals and index pulse • 16-bit up/down position counter • Count direction status • Position Measurement (x2 and x4) mode • ...
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... Quadrature Encoder Interface Logic A typical incremental (a.k.a. optical) encoder has three outputs: Phase A, Phase B and an index pulse. These signals are useful and often required in position and speed control of ACIM and SR motors. The two channels, Phase A (QEA) and Phase B (QEB), have a unique relationship ...
Page 91
... Timer register. When UPDN = 1, the timer will count up. When UPDN = 0, the timer will count down. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 In addition, control bit, UDSRC (QEICON<0>), determines whether the timer count direction state is based on the logic state written into the UPDN control/Status bit (QEICON< ...
Page 92
... TIMER OPERATION DURING CPU IDLE MODE When the CPU is placed in the Idle mode and the QEI module is configured in the 16-bit Timer mode, the 16-bit timer will operate if the (QEICON<13> This bit defaults to a logic ‘0’ upon executing POR and BOR. For halting the timer module during the CPU Idle mode, QEISIDL should be set to ‘ ...
Page 93
TABLE 14-1: QEI REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Name QEICON 0122 CNTERR — QEISIDL INDX UPDN DFLTCON 0124 — — — — — POSCNT 0126 MAXCNT 0128 Legend: ...
Page 94
... NOTES: DS70149D-page 94 © 2008 Microchip Technology Inc. ...
Page 95
... Switched Reluctance (SR) Motor • Brushless DC (BLDC) Motor • Uninterruptible Power Supply (UPS) © 2008 Microchip Technology Inc. dsPIC30F5015/5016 The PWM module has the following features: • 8 PWM I/O pins with 4 duty cycle generators • 16-bit resolution • ‘On-the-Fly’ PWM frequency changes • ...
Page 96
... FIGURE 15-1: PWM MODULE BLOCK DIAGRAM PWMCON1 PWMCON2 DTCON1 DTCON2 FLTACON FLTBCON OVDCON PTMR Comparator PTPER PTPER Buffer PTCON Comparator SEVTDIR SEVTCMP PWM Time Base Note: Details of PWM Generator #1, #2 and #3 not shown for clarity. DS70149D-page 96 PWM Enable and Mode SFRs ...
Page 97
... The interrupt signals generated by the PWM time base depend on the mode selection bits (PTMOD<1:0>) and the postscaler bits (PTOPS<3:0>) in the PTCON SFR. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 15.1.1 FREE-RUNNING MODE In Free-Running mode, the PWM time base counts upwards until the value in the Time Base Period register (PTPER) is matched ...
Page 98
... DOUBLE UPDATE MODE In the Double Update mode (PTMOD<1:0> = 11), an interrupt event is generated each time the PTMR register is equal to zero, as well as each time a period match occurs. The postscaler selection bits have no effect in this mode of the timer. The Double Update mode provides two additional functions to the user ...
Page 99
... LSb of a Duty Cycle register determines whether the PWM edge occurs in the beginning. Thus, the PWM resolution is effectively doubled. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 15.5.1 DUTY CYCLE REGISTER BUFFERS The four PWM Duty Cycle registers are double-buffered to allow glitchless updates of the PWM outputs. For each ...
Page 100
... Complementary PWM Operation In the Complementary mode of operation, each pair of PWM outputs is obtained by a complementary PWM signal. A dead time may be optionally inserted during device switching, when both outputs are inactive for a short period (Refer to Section 15.7 “Dead-Time Generators”). In Complementary mode, the duty cycle comparison units are assigned to the PWM outputs as follows: • ...
Page 101
... PTMR register is cleared, all active PWM I/O pins are driven to the inactive state, the PTEN bit is cleared and an interrupt is generated. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 Time selected by DTSxI bit ( 15.10 PWM Output Override The PWM output override bits allow the user to manually drive the PWM I/O pins to specified logic states, independent of the duty cycle comparison units ...
Page 102
... PWM Output and Polarity Control There are three device Configuration bits associated with the PWM module that provide PWM output pin control: • HPOL Configuration bit • LPOL Configuration bit • PWMPIN Configuration bit These three bits in the FBORPOR Configuration register (see Section 20.6 “ ...
Page 103
... PWM time base. The SEVTDIR control bit has no effect unless the PWM time base is configured for an Up/Down Counting mode. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 15.14.1 SPECIAL EVENT TRIGGER POSTSCALER The PWM special event trigger has a postscaler that allows a 1:1 to 1:16 postscale ratio. The postscaler is configured by writing the SEVOPS< ...
Page 104
TABLE 15-2: 8-OUTPUT PWM REGISTER MAP SFR Name Addr Bit 15 Bit 14 Bit 13 Bit 12 PTCON 01C0 PTEN — PTSIDL — PTMR 01C2 PTDIR PTPER 01C4 — SEVTCMP 01C6 SEVTDIR PWMCON1 01C8 — — — — PTMOD4 PTMOD3 ...
Page 105
... Microchip Technology Inc. dsPIC30F5015/5016 Transmit writes are also double-buffered. The user writes to SPIxBUF. When the master or slave transfer is completed, the contents of the Shift register (SPIxSR) is moved to the receive buffer. If any ...
Page 106
... FIGURE 16-1: SPI BLOCK DIAGRAM Read SPIxBUF Receive SDIx bit 0 SDOx SS & FSYNC Control SSx SCKx Note FIGURE 16-2: SPI MASTER/SLAVE CONNECTION SPI Master Serial Input Buffer (SPIxBUF) Shift Register (SPIxSR) MSb PROCESSOR 1 Note DS70149D-page 106 Internal Data Bus Write ...
Page 107
... Therefore, when the SSx pin is asserted low again, transmission/reception will begin at the MSb, even if SSx had been deasserted in the middle of a transmit/receive. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 16.4 SPI Operation During CPU Sleep Mode During Sleep mode, the SPI module is shutdown. If the ...
Page 108
TABLE 16-1: SPI1 REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name SPI1STAT 0220 SPIEN — SPISIDL — SPI1CON 0222 — FRMEN SPIFSD — DISSDO MODE16 SPI1BUF 0224 Legend: — = unimplemented bit, ...
Page 109
... Thus, the I C module can operate either as a slave master bus. FIGURE 17-1: PROGRAMMER’S MODEL bit 15 bit 15 © 2008 Microchip Technology Inc. dsPIC30F5015/5016 17.1.1 VARIOUS I The following types • Slave operation with 7-bit address 2 • Slave operation with 10-bit address 2 • ...
Page 110
... FIGURE 17-2: I C™ BLOCK DIAGRAM Shift SCL Clock SDA Match Detect Stop bit Detect Start, Restart, Stop bit Generate Acknowledge Shift Clock DS70149D-page 110 I2CRCV I2CRSR LSB Addr_Match I2CADD Start and Collision Detect Generation Clock Stretching I2CTRN LSB Reload ...
Page 111
... ACK received from the master. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 17.3.2 SLAVE RECEPTION If the R_W bit received is a ‘0’ during an address match, then Receive mode is initiated. Incoming bits are sampled on the rising edge of SCL ...
Page 112
... MODE SLAVE TRANSMISSION Once a slave is addressed in this fashion, with the full 10-bit address (we will refer to this state as “PRIOR_ADDR_MATCH”), the master can begin sending data bytes for a slave reception operation. 17.4.2 10-BIT MODE SLAVE RECEPTION Once addressed, the master can generate a Repeated ...
Page 113
... Generate a Stop condition on SDA and SCL. 2 • Configure the I C port to receive data. • Generate an ACK condition at the end of a received byte of data. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 2 17. Master Operation The master device generates all of the serial clock 2 C Slave pulses and the Start and Stop conditions ...
Page 114
... As per the I C standard, FSCK may be 100 kHz or 400 kHz. However, the user can specify any baud rate MHz. I2CBRG values of ‘0’ or ‘1’ are illegal. EQUATION 17-1: SERIAL CLOCK RATE F F ⎛ ⎞ ------------ - -------------------------- - I2CBRG = – ⎝ ⎠ ...
Page 115
TABLE 17-2: I C™ REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 — — — — I2CRCV 0200 — — — — I2CTRN 0202 — — — — I2CBRG 0204 — I2CCON 0206 ...
Page 116
... NOTES: DS70149D-page 116 © 2008 Microchip Technology Inc. ...
Page 117
... UTXBRK Data UxTX Parity Note © 2008 Microchip Technology Inc. dsPIC30F5015/5016 18.1 UART Module Overview The key features of the UART module are: • Full-duplex 9-bit data communication • Even, Odd or No Parity options (for 8-bit data) • One or two Stop bits • ...
Page 118
... FIGURE 18-2: UART RECEIVER BLOCK DIAGRAM LPBACK From UxTX 1 UxRX 0 · Start bit Detect · Parity Check · Stop bit Detect · Shift Clock Generation · Wake Logic Note DS70149D-page 118 Internal Data Bus 16 Read Write URX8 UxRXREG Low Byte Receive Buffer Control – ...
Page 119
... The STSEL bit determines whether one or two Stop bits will be used during data transmission. The default (Power-on) setting of the UART is 8 bits, no parity, 1 Stop bit (typically represented 1). © 2008 Microchip Technology Inc. dsPIC30F5015/5016 18.3 Transmitting Data 18.3.1 TRANSMITTING IN 8-BIT DATA MODE ...
Page 120
... TRANSMIT INTERRUPT The transmit interrupt flag (U1TXIF) is located in the corresponding Interrupt Flag register. The transmitter generates an edge to set the UxTXIF bit. The condition for generating the interrupt depends on UTXISEL control bit UTXISEL = 0, an interrupt is generated when a word is transferred from the Transmit buffer to the Transmit Shift register (UxTSR) ...
Page 121
... No further reception can occur until a Stop bit is received. Note that RIDLE goes high when the Stop bit has not been received yet. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 18.6 Address Detect Mode Setting the ADDEN bit (UxSTA<5>) enables this special mode, in which a 9th bit (URX8) value of ‘ ...
Page 122
... Auto-Baud Support To allow the system to determine baud rates of received characters, the input can be optionally linked to a selected capture input. To enable this mode, the user must program the input capture module to detect the falling and rising edges of the Start bit. ...
Page 123
TABLE 18-1: UART1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 U1MODE 020C UARTEN — USIDL — U1STA 020E UTXISEL — — — UTXBRK UTXEN U1TXREG 0210 — — — — U1RXREG ...
Page 124
... NOTES: DS70149D-page 124 © 2008 Microchip Technology Inc. ...
Page 125
... Programmable Loopback mode supports self-test operation • Signaling via interrupt capabilities for all CAN receiver and transmitter error states © 2008 Microchip Technology Inc. dsPIC30F5015/5016 • Programmable clock source • Programmable link to timer module for time-stamping and network synchronization • Low-power Sleep and Idle mode The CAN bus module consists of a protocol engine, and message buffering/control ...
Page 126
... FIGURE 19-1: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM BUFFERS TXB0 TXB1 Message Queue Control Transmit Byte Sequencer PROTOCOL ENGINE Transmit Logic (1) CiTX Note refers to CAN1 module DS70149D-page 126 Acceptance Mask TXB2 RXM0 A Acceptance Filter c RXF0 c e Acceptance Filter p RXF1 ...
Page 127
... Disable mode. The I/O pins will revert to normal I/O function when the module is in the Module Disable mode. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 The module can be programmed to apply a low-pass filter function to the CiRX input line while the module or the CPU is in Sleep mode. The WAKFIL bit (CiCFG2< ...
Page 128
... Message Reception 19.4.1 RECEIVE BUFFERS The CAN bus module has 3 receive buffers. However, one of the receive buffers is always committed to mon- itoring the bus for incoming messages. This buffer is called the Message Assembly Buffer (MAB). So there are 2 receive buffers visible, RXB0 and RXB1, that can ...
Page 129
... TXERR (CiTXnCON<4>) flag automatically cleared. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 Setting the TXREQ bit simply flags a message buffer as enqueued for transmission. When the module detects an available bus, it begins transmitting the message which has been determined to have the highest priority. If the transmission completes successfully on the first attempt, the TXREQ bit is cleared automatically and an interrupt is generated if TXIE was set ...
Page 130
... TRANSMIT INTERRUPTS Transmit interrupts can be divided into 2 major groups, each including various conditions that generate interrupts: • Transmit Interrupt At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. Reading the TXnIF flags will indicate which transmit buffer is available and caused the interrupt ...
Page 131
... The following requirement must be fulfilled while setting the lengths of the Phase Segments: • Propagation Segment + Phase1 Seg > = Phase2 Seg © 2008 Microchip Technology Inc. dsPIC30F5015/5016 19.6.5 SAMPLE POINT The sample point is the point of time at which the bus level is read and interpreted as the value of that respec- tive bit ...
Page 132
TABLE 19-1: CAN1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 — — — C1RXF0SID 0300 C1RXF0EIDH 0302 — — — — C1RXF0EIDL 0304 Receive Acceptance Filter 0 Extended Identifier<5:0> — — — C1RXF1SID ...
Page 133
TABLE 19-1: CAN1 REGISTER MAP (CONTINUED) SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 C1TX1B2 0358 Transmit Buffer 1 Byte 3 C1TX1B3 035A Transmit Buffer 1 Byte 5 C1TX1B4 035C Transmit Buffer 1 Byte 7 C1TX1CON ...
Page 134
... NOTES: DS70149D-page 134 © 2008 Microchip Technology Inc. ...
Page 135
... In the Idle mode, the clock sources are still active, but the CPU is shut-off. The RC oscillator option saves system cost, while the LP crystal option saves power. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 20.1 Oscillator System Overview The dsPIC30F oscillator system has the following modules and features: • ...
Page 136
... TABLE 20-1: OSCILLATOR OPERATING MODES Oscillator Mode XTL 200 kHz-4 MHz crystal on OSC1:OSC2 XT 4 MHz-10 MHz crystal on OSC1:OSC2 XT w/PLL 4x 4 MHz-10 MHz crystal on OSC1:OSC2, 4x PLL enabled XT w/PLL 8x 4 MHz-10 MHz crystal on OSC1:OSC2, 8x PLL enabled XT w/PLL 16x 4 MHz-7.5 MHz crystal on OSC1:OSC2, 16x PLL enabled ...
Page 137
... OSCILLATOR SYSTEM BLOCK DIAGRAM OSC1 Primary Oscillator OSC2 TUN<4:0> 5 Internal Fast RC Oscillator (FRC) POR Done SOSCO 32 kHz LP Oscillator SOSCI © 2008 Microchip Technology Inc. dsPIC30F5015/5016 F PLL PLL x4, x8, x16 PLL Lock Primary Osc Primary Oscillator Stability Detector Oscillator Start-up Clock Timer ...
Page 138
... Oscillator Configurations 20.2.1 INITIAL CLOCK SOURCE SELECTION While coming out of Power-on Reset or Brown-out Reset, the device selects its clock source based on: a) FOS<2:0> Configuration bits that select one of four oscillator groups. b) AND FPR<4:0> Configuration bits that select one of 16 oscillator choices within the primary group ...
Page 139
... The state of this signal is reflected in the read-only LOCK bit in the OSCCON register. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 20.2.5 FAST RC OSCILLATOR (FRC) The FRC oscillator is a fast (7.37 MHz ±2% nominal) internal RC oscillator ...
Page 140
... LOW-POWER RC OSCILLATOR (LPRC) The LPRC oscillator is a component of the Watchdog Timer (WDT) and oscillates at a nominal frequency of 512 kHz. The LPRC oscillator is the clock source for the Power-up Timer (PWRT) circuit, WDT and clock monitor circuits. It may also be used to provide a low ...
Page 141
... Rise DD Detect V DD Brown-out Reset BOREN Trap Conflict Illegal Opcode/ Uninitialized W Register © 2008 Microchip Technology Inc. dsPIC30F5015/5016 20.3 Reset The PIC18F1220/1320 differentiates between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during Sleep d) Watchdog Timer (WDT) Reset (during normal ...
Page 142
... POR: POWER-ON RESET A power-on event will generate an internal POR pulse when a V rise is detected. The Reset pulse will occur DD at the POR circuit threshold voltage (V nominally 1.85V. The device supply characteristics must meet specified starting voltage and rise rate requirements. The POR pulse will reset a POR timer and place the device in the Reset state ...
Page 143
... If the FSCM is disabled and the system clock has not started, the device will frozen state at the Reset vector until the system clock starts. From the user’s perspective, the device will appear Reset until a system clock is available. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 T OST T PWRT 20.3.2 ...
Page 144
... Concurrently, the POR time-out (T POR time-out (T ) will be applied before the internal PWRT Reset is released and a crystal oscillator PWRT is being used, then a nominal delay applied. The total delay POR FSCM The BOR Status bit (RCON<1>) will be set to indicate that a BOR has occurred. The BOR circuit, if enabled, ...
Page 145
... Trap Reset 0x000000 Illegal Operation Reset 0x000000 Legend unchanged Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR ...
Page 146
... Watchdog Timer (WDT) 20.4.1 WATCHDOG TIMER OPERATION The primary function of the Watchdog Timer (WDT reset the processor in the event of a software malfunction. The WDT is a free-running timer, which runs off an on-chip RC oscillator, requiring no external component. Therefore, the WDT timer will continue to operate even if the main processor clock (e ...
Page 147
... WDTO Status bits are both set. Unlike wake-up from Sleep, there are no time delays involved in wake-up from Idle. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 20.6 Device Configuration Registers The Configuration bits in each device Configuration register specify some of the device modes and are ...
Page 148
... Peripheral Module Disable (PMD) Registers The Peripheral Module Disable (PMD) registers provide a method to disable a peripheral module by stopping all clock sources supplied to that module. When a peripheral is disabled via the appropriate PMD control bit, the peripheral minimum power consumption state. The control and status registers ...
Page 149
... TABLE 20-7: SYSTEM INTEGRATION REGISTER MAP FOR dsPIC30F5015/5016 SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name RCON 0740 TRAPR IOPUWR BGST — — OSCCON 0742 — COSC<2:0> — 0744 — — — — — OSCTUN PMD1 0770 T5MD T4MD T3MD T2MD T1MD QEIMD PWMMD — ...
Page 150
... NOTES: DS70149D-page 150 © 2008 Microchip Technology Inc. ...
Page 151
... REF REF feature of being able to operate while the device is in Sleep mode. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 The ADC module has six 16-bit registers: • A/D Control Register1 (ADCON1) • A/D Control Register2 (ADCON2) • A/D Control Register3 (ADCON3) • A/D Input Select Register (ADCHS) • ...
Page 152
... AN11 AN11 AN12 AN12 AN13 AN13 AN14 AN14 AN15 AN15 AN1 Note multiplexed with AN0 in the dsPIC30F5015 variant. REF multiplexed with AN1 in the dsPIC30F5015 variant. REF DS70149D-page 152 + CH1 ADC S/H - 10-bit Result + CH2 S/H - 16-word, 10-bit Dual Port + CH3 S/H ...
Page 153
... The channels are then converted sequentially. Obviously, if there is only 1 channel selected, the SIMSAM bit is not applicable. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 The CHPS bits selects how many channels are sampled. This can vary from channels. If CHPS selects 1 channel, the CH0 channel will be sampled at the sample clock and converted ...
Page 154
... Programming the Start of Conversion Trigger The conversion trigger will terminate acquisition and start the requested conversions. The SSRC<2:0> bits select the source of the conversion trigger. The SSRC bits provide for up to five alternate sources of conversion trigger. When SSRC<2:0> = 000, the conversion trigger is under software control ...
Page 155
... Up to 256. 300 ksps Note 1: External V - and V + pins must be used for correct operation. See Figure 21-2 for recommended REF REF circuit. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 R Max V Temperature S DD 500Ω 4.5V to 5.5V -40°C to +85°C 500Ω 4.5V to 5.5V -40° ...
Page 156
... The analog input multiplexer must be configured so that the same input pin is connected to both sample and hold channels. The ADC converts the value held on one S/H channel, while the second S/H channel acquires a new input sample. DS70149D-page 156 dsPIC30F5015 21.7.1.2 The ADC can also be used to sample multiple analog inputs using multiple sample and hold channels ...
Page 157
... X 750,000 by writing to the ADCS<5:0> control bits in the ADCON3 register • Configure the sampling time writing: SAMC<4:0> = 00010 © 2008 Microchip Technology Inc. dsPIC30F5015/5016 21.7.3 600 ksps CONFIGURATION GUIDELINE The configuration for 600 ksps operation is dependent on whether a single input pin sampled or whether multiple pins will be sampled. ...
Page 158
... ADC Acquisition Requirements The analog input model of the 10-bit ADC is shown in Figure 21-3. The total sampling time for the ADC is a function of the internal amplifier settling time, device V and the holding capacitor charge time. DD For the ADC to meet its specified accuracy, the charge ...
Page 159
... Integer 0 © 2008 Microchip Technology Inc. dsPIC30F5015/5016 If the A/D interrupt is enabled, the device will wake-up from Sleep. If the A/D interrupt is not enabled, the A/D module will then be turned off, although the ADON bit will remain set ...
Page 160
... Configuring Analog Port Pins The use of the ADPCFG and TRIS registers control the operation of the ADC port pins. The port pins that are desired as analog inputs must corresponding TRIS bit set (input). If the TRIS bit is cleared (output), the digital output level (V will be converted ...
Page 161
TABLE 21-2: ADC REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 ADCBUF0 0280 — — — — ADCBUF1 0282 — — — — ADCBUF2 0284 — — — — ADCBUF3 0286 — — — ...
Page 162
... NOTES: DS70149D-page 162 © 2008 Microchip Technology Inc. ...
Page 163
... The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2008 Microchip Technology Inc. dsPIC30F5015/5016 Most bit oriented instructions (including simple rotate/shift instructions) have two operands: • The W register (with or without an address modifier) or file register (specified by the value of ‘ ...
Page 164
... Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a NOP. Notable exceptions are the ...
Page 165
... Y data space prefetch address register for DSP instructions Wy ∈ {[W10 [W10 [W10 [W10], [W10 [W10 [W10 [W11 [W11 [W11 [W11], [W11 [W11 [W11 [W11+W12], none} Y data space prefetch destination register for DSP instructions ∈ {W4..W7} Wyd © 2008 Microchip Technology Inc. dsPIC30F5015/5016 Description DS70149D-page 165 ...
Page 166
... TABLE 22-2: INSTRUCTION SET OVERVIEW Base Assembly Instr Assembly Syntax Mnemonic # 1 ADD ADD Acc ADD f ADD f,WREG ADD #lit10,Wn ADD Wb,Ws,Wd ADD Wb,#lit5,Wd ADD Wso,#Slit4,Acc 2 ADDC ADDC f ADDC f,WREG ADDC #lit10,Wn ADDC Wb,Ws,Wd ADDC Wb,#lit5,Wd 3 AND AND f AND f,WREG ...
Page 167
... ED ED Wm*Wm,Acc,Wx,Wy,Wxd 33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd 34 EXCH EXCH Wns,Wnd © 2008 Microchip Technology Inc. dsPIC30F5015/5016 # of Description words Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws<Wb> Bit Test Ws<Wb> Bit Test then Set f Bit Test then Set ...
Page 168
... TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 35 FBCL FBCL Ws,Wnd 36 FF1L FF1L Ws,Wnd 37 FF1R FF1R Ws,Wnd 38 GOTO GOTO Expr GOTO Wn 39 INC INC f INC f,WREG INC Ws,Wd 40 INC2 INC2 f INC2 f,WREG INC2 Ws,Wd 41 IOR IOR ...
Page 169
... SFTAC Acc,#Slit6 f,WREG SL Ws,Wd SL Wb,Wns,Wnd SL Wb,#lit5,Wnd © 2008 Microchip Technology Inc. dsPIC30F5015/5016 # of Description words Negate Accumulator WREG = Operation No Operation Pop f from Top-of-Stack (TOS) Pop from Top-of-Stack (TOS) to Wdo Pop from Top-of-Stack (TOS) to W(nd):W(nd+1) Pop Shadow Registers Push f to Top-of-Stack (TOS) ...
Page 170
... TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 72 SUB SUB Acc SUB f SUB f,WREG SUB #lit10,Wn SUB Wb,Ws,Wd SUB Wb,#lit5,Wd 73 SUBB SUBB f SUBB f,WREG SUBB #lit10,Wn SUBB Wb,Ws,Wd SUBB Wb,#lit5,Wd 74 SUBR SUBR f SUBR f,WREG SUBR Wb,Ws,Wd ...
Page 171
... MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2008 Microchip Technology Inc. dsPIC30F5015/5016 23.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market ...
Page 172
... MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging ...
Page 173
... Microchip Technology Inc. dsPIC30F5015/5016 23.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, ...
Page 174
... PICSTART Plus Development Programmer The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages pins. ...
Page 175
... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 (1) (except V and MCLR) ...
Page 176
... DC Characteristics TABLE 24-1: OPERATING MIPS VS. VOLTAGE FOR dsPIC30F5015 V Range Temp Range DD (in Volts) (in °C) 4.5-5.5 -40 to +85 4.5-5.5 -40 to +125 3.0-3.6 -40 to +85 3.0-3.6 -40 to +125 2.5-3.0 -40 to +85 TABLE 24-2: OPERATING MIPS VS. VOLTAGE FOR dsPIC30F5016 V Range Temp Range DD (in Volts) (in °C) 4 ...
Page 177
... Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing. 3: This is the limit to which V DD © 2008 Microchip Technology Inc. dsPIC30F5015/5016 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) Min Typ Max 2.5 — ...
Page 178
... TABLE 24-6: DC CHARACTERISTICS: OPERATING CURRENT (I DC CHARACTERISTICS Parameter (1) Typical Max No. (2) Operating Current ( DC31a 5.6 10 DC31b 5.7 10 DC31c 5.5 10 DC31e 14 23 DC31f 15 23 DC31g 15 23 DC30a 10 21 DC30b 12 21 DC30c 14 21 DC30e 23 38 DC30f 24 38 DC30g 25 38 DC23a 30 50 DC23b ...
Page 179
... Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Base I current is measured with Core off, Clock on and all modules turned off. IDLE © 2008 Microchip Technology Inc. dsPIC30F5015/5016 ) IDLE Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial ...
Page 180
... TABLE 24-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (I DC CHARACTERISTICS Parameter (1) Typical Max No. (2) Power Down Current ( DC60a 0.2 — DC60b 0.7 40 DC60c 12 65 DC60e 0.4 — DC60f 1.7 55 DC60g 16 90 DC61a 10 30 DC61b 12 30 DC61c 12 30 DC61e 20 40 DC61f 22 40 DC61g 23 40 ...
Page 181
... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 5: Negative current is defined as current sourced by the pin. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) Min ...
Page 182
... TABLE 24-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS DC CHARACTERISTICS Param Symbol Characteristic No. V Output Low Voltage OL DO10 I/O ports DO16 OSC2/CLKO ( Osc mode) V Output High Voltage OH DO20 I/O ports DO26 OSC2/CLKO ( Osc mode) Capacitive Loading Specs (2) on Output Pins DO50 C 2 OSC2/SOSC2 pin ...
Page 183
... Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 2: These parameters are characterized but not tested in manufacturing. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial Operating temperature A -40° ...
Page 184
... AC Characteristics and Timing Parameters The information contained in this section defines dsPIC30F AC characteristics and timing parameters. TABLE 24-13: TEMPERATURE AND VOLTAGE SPECIFICATIONS – CHARACTERISTICS FIGURE 24-2: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSC2 ...
Page 185
... Measurements are taken ERC modes. The CLKO signal is measured on the OSC2 pin. CLKO is low for the Q1-Q2 period (1/2 T © 2008 Microchip Technology Inc. dsPIC30F5015/5016 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) ...
Page 186
... TABLE 24-15: PLL CLOCK TIMING SPECIFICATIONS (V AC CHARACTERISTICS Param Symbol Characteristic No. OS50 F PLL Input Frequency Range PLLI OS51 F On-Chip PLL Output SYS OS52 T PLL Start-up Time (Lock Time) LOC Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested ...
Page 187
... Mode EC 0.200 Note 1: Assumption: Oscillator Postscaler is divide Instruction Execution Cycle Time Instruction Execution Frequency: MIPS = (F cycle). © 2008 Microchip Technology Inc. dsPIC30F5015/5016 (3) (3) MIPS MIPS (2) (μsec) w/o PLL w PLL x4 20.0 0.05 — 1.0 1.0 4.0 0.4 2.5 10.0 0.16 6.25 — ...
Page 188
... TABLE 24-18: AC CHARACTERISTICS: INTERNAL FRC ACCURACY Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature Param Characteristic No. Internal FRC Accuracy @ FRC Freq. = 7.37 MHz OS63 FRC Note 1: Frequency calibrated at 25°C and 5V. TUN bits can be used to compensate for temperature drift. ...
Page 189
... Measurements are taken in RC mode and EC mode where CLKO output These parameters are characterized but not tested in manufacturing. 4: Data in “Typ” column is at 5V, 25°C unless otherwise stated. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 DI35 DI40 New Value DO31 DO32 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
Page 190
... FIGURE 24-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS V DD SY12 MCLR Internal POR SY11 PWRT Time-out SY30 OSC Time-out Internal Reset Watchdog Timer Reset I/O Pins SY35 FSCM Delay Note: Refer to Figure 24-2 for load conditions. ...
Page 191
... AC CHARACTERISTICS Param Symbol Characteristic No. SY40 T Band Gap Start-up Time BGAP Note 1: These parameters are characterized but not tested in manufacturing. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) (2) Min Typ Max 2 — — ...
Page 192
... FIGURE 24-7: TIMER1 AND 5 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK TMRX Note: Refer to Figure 24-2 for load conditions. TABLE 24-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. TA10 T H TxCK High Time TX TA11 T L TxCK Low Time TX TA15 T P TxCK Input Period Synchronous, ...
Page 193
... TxCK Low Time TC15 TtxP TxCK Input Period Synchronous, TC20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment © 2008 Microchip Technology Inc. dsPIC30F5015/5016 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T Min Typ Synchronous, 0 — ...
Page 194
... FIGURE 24-8: TIMERQ (QEI MODULE) EXTERNAL CLOCK TIMING CHARACTERISTICS QEB POSCNT TABLE 24-26: QEI MODULE EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. TQ10 TtQH TQCK High Time TQ11 TtQL TQCK Low Time TQ15 TtQP TQCP Input Period TQ20 T Delay from External TxCK Clock ...
Page 195
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 IC10 IC11 IC15 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
Page 196
... FIGURE 24-11: OC/PWM MODULE TIMING CHARACTERISTICS OCFA/OCFB OC15 OCx TABLE 24-29: SIMPLE OC/PWM MODE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. OC15 T Fault Input to PWM I/O FD Change OC20 T Fault Input Pulse Width FLT Note 1: These parameters are characterized but not tested in manufacturing. ...
Page 197
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 MP30 MP11 MP10 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
Page 198
... FIGURE 24-14: QEA/QEB INPUT CHARACTERISTICS QEA (input) QEB (input) QEB Internal TABLE 24-31: QUADRATURE DECODER TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. TQ30 T L Quadrature Input Low Time QU TQ31 T H Quadrature Input High Time QU TQ35 T IN Quadrature Input Period QU TQ36 T P Quadrature Phase Period ...
Page 199
... Alignment of index pulses to QEA and QEB is shown for position counter reset timing only. Shown for forward direction only (QEA leads QEB). Same timing applies for reverse direction (QEA lags QEB) but index pulse recognition occurs on falling edge. © 2008 Microchip Technology Inc. dsPIC30F5015/5016 TQ50 TQ55 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
Page 200
... FIGURE 24-16: SPI MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP11 SCKx (CKP = 1) SP35 SDOx SP31 SDIx MSb IN SP40 SP41 Note: Refer to Figure 24-2 for load conditions. TABLE 24-33: SPI MASTER MODE (CKE = 0) TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No ...