AT91SAM9R64-CU-999 Atmel, AT91SAM9R64-CU-999 Datasheet - Page 742
AT91SAM9R64-CU-999
Manufacturer Part Number
AT91SAM9R64-CU-999
Description
IC MCU ARM9 64K SRAM 144LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9R64-CU.pdf
(903 pages)
Specifications of AT91SAM9R64-CU-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
240MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, POR, PWM, WDT
Number Of I /o
49
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
72K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 3x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
SPI, TWI, UART
Maximum Clock Frequency
240 MHz
Number Of Programmable I/os
118
Operating Supply Voltage
1.65 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9RL-EK
Minimum Operating Temperature
- 40 C
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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41.4.8.2
Figure 41-6. NYET Example with Two Endpoint Banks
41.4.8.3
41.4.8.4
41.4.8.5
742
AT91SAM9R64/RL64 Preliminary
t = 0
NYET
Data IN
Bulk IN or Interrupt IN
Bulk IN or Interrupt IN: Sending a Packet Under Application Control (Device to Host)
data 0 ACK
Bank 1
Bank 0
t = 125 µs
Thus, firmware must detect RX_SETUP polling UDPHS_EPTSTAx or catching an interrupt, read
the setup packet in the FIFO, then clear the RX_SETUP bit in the UDPHS_EPTCLRSTA register
to acknowledge the setup stage.
If STALL_SNT was set to 1, then this bit is automatically reset when a setup token is detected by
the device. Then, the device still accepts the setup stage. (See
page
NYET is a High Speed only handshake. It is returned by a High Speed endpoint as part of the
PING protocol.
High Speed devices must support an improved NAK mechanism for Bulk OUT and control end-
points (except setup stage). This mechanism allows the device to tell the host whether it has
sufficient endpoint space for the next OUT transfer (see USB 2.0 spec 8.5.1 NAK Limiting via
Ping Flow Control).
The NYET/ACK response to a High Speed Bulk OUT transfer and the PING response are auto-
matically handled by hardware in the UDPHS_EPTCTLx register (except when the user wants to
force a NAK response by using the NYET_DIS bit).
If the endpoint responds instead to the OUT/DATA transaction with an NYET handshake, this
means that the endpoint accepted the data but does not have room for another data payload.
The host controller must return to using a PING token until the endpoint indicates it has space
available.
Data IN packets are sent by the device during the data or the status stage of a control transfer or
during an (interrupt/bulk/isochronous) IN transfer. Data buffers are sent packet by packet under
the control of the application or under the control of the DMA channel.
There are three ways for an application to transfer a buffer in several packets over the USB:
The application can write one or several banks.
E
F
• packet by packet (see
•
• DMA (see
64
data 1 NYET
753).
KB (see
Bank 1
Bank 0
41.4.8.6
t = 250 µs
41.4.8.5
E'
F
Bank 1
Bank 0
PING ACK
below)
below)
F
E
41.4.8.5
t = 375 µs
Bank 1
Bank 0
below)
data 0 NYET
F
E
Bank 1
Bank 0
t = 500 µs
F
F
PING NACK
Bank 1
Bank 0
E'
F
t = 625 µs
Section 41.4.8.15 “STALL” on
Bank 1
Bank 0
PING ACK
E
F
6289C–ATARM–28-May-09
E: empty
E': begin to empty
F: full
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