ATSAM3S2AA-MU Atmel, ATSAM3S2AA-MU Datasheet - Page 99
ATSAM3S2AA-MU
Manufacturer Part Number
ATSAM3S2AA-MU
Description
IC MCU 32BIT 128KB FLASH 48QFN
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S2AA-MU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 8x10/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
- Current page: 99 of 1118
- Download datasheet (24Mb)
10.12.7
10.12.7.1
10.12.7.2
10.12.7.3
10.12.7.4
10.12.7.5
6500C–ATARM–8-Feb-11
PUSH
PUSH
POP
PUSH and POP
Syntax
Operation
Restrictions
Condition flags
Examples
{R0,R4-R7}
{R2,LR}
{R0,R10,PC}
Push registers onto, and pop registers off a full-descending stack.
where:
cond
reglist
It must be comma separated if it contains more than one register or register range.
PUSH and POP are synonyms for STMDB and LDM (or LDMIA) with the memory addresses for
the access based on SP, and with the final address for the access written back to the SP. PUSH
and POP are the preferred mnemonics in these cases.
PUSH stores registers on the stack in order of decreasing the register numbers, with the highest
numbered register using the highest memory address and the lowest numbered register using
the lowest memory address.
POP loads registers from the stack in order of increasing register numbers, with the lowest num-
bered register using the lowest memory address and the highest numbered register using the
highest memory address.
See
In these instructions:
When PC is in reglist in a POP instruction:
These instructions do not change the flags.
• reglist must not contain SP
• for the PUSH instruction, reglist must not contain PC
• for the POP instruction, reglist must not contain PC if it contains LR.
• bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch occurs to
• if the instruction is conditional, it must be the last instruction in the IT block.
this halfword-aligned address
PUSH{cond} reglist
POP{cond} reglist
“LDM and STM” on page 97
is an optional condition code, see
is a non-empty list of registers, enclosed in braces. It can contain register ranges.
for more information.
“Conditional execution” on page
SAM3S Preliminary
84.
99
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