AT89C5132-RORUL Atmel, AT89C5132-RORUL Datasheet - Page 64
![MCU 8051 FLASH USB 80TQFP](/photos/12/13/121358/313-80-tqfp_sml.jpg)
AT89C5132-RORUL
Manufacturer Part Number
AT89C5132-RORUL
Description
MCU 8051 FLASH USB 80TQFP
Manufacturer
Atmel
Series
AT89C513xr
Specifications of AT89C5132-RORUL
Core Processor
C52X2
Core Size
8-Bit
Speed
20MHz
Connectivity
IDE/ATAPI, I²C, MMC, PCM, SPI, UART/USART, USB
Peripherals
I²S, POR, WDT
Number Of I /o
44
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 2x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Company
Part Number
Manufacturer
Quantity
Price
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Figure 14-6. Voice or Sound Mode Audio Flows
Note:
14.7
64
1. An under-run occurrence signifies that the C51 core did not respond to the previous sample request interrupt. It may never
Registers
AT89C5132
occur for a correct voice/sound generation. It is the user’s responsibility to mask it or not.
Program Audio Clock
Voice/Song Mode
Enable DAC System
Configure Interface
JUST4:0 = XXXXXb
Configuration
DUP1:0 = XX
AUDEN = 1
DSIZ = X
HLR = X
POL = X
Clock
Table 51. AUDCON0 Register
AUDCON0 (S:9Ah) – Audio Interface Control Register 0
Reset Value = 0000 1000b
Table 52. AUDCON1 Register
AUDCON1 (S:9Bh) – Audio Interface Control Register 1
Bit Number
JUST4
7-3
7
2
1
0
7
–
Set MSREQ & MUDRN
Load 8 Samples in the
Mnemonic
Enable Interrupt
JUST4:0
Wait for DAC
Audio Buffer
JUST3
Enable Time
DSIZ
POL
HLR
EAUD = 1
Bit
6
6
–
Description
Audio Stream Justification Bits
Refer to Section "Data Converter", page 61 for bits description.
DSEL Signal Output Polarity
Set to output the left channel on high level of DSEL output (PCM mode).
Clear to output the left channel on the low level of DSEL output (I
Audio Data Size
Set to select 32-bit data output format.
Clear to select 16-bit data output format.
High/Low Rate Bit
Set by software when the PLL clock frequency is 384·Fs.
Clear by software when the PLL clock frequency is 256·Fs.
MSREQ
JUST2
1
5
5
MUDRN
JUST1
4
4
Load 4 Samples in the
Service Routine
Sample Request?
Audio Interrupt
Audio Buffer
SREQ = 1?
JUST0
3
3
-
DUP1
POL
2
2
Under-run Condition
DUP0
DSIZ
2
1
S mode).
1
1
4173E–USB–09/07
AUDEN
HLR
0
0
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