AT91SAM7L128-AU Atmel, AT91SAM7L128-AU Datasheet - Page 143
AT91SAM7L128-AU
Manufacturer Part Number
AT91SAM7L128-AU
Description
MCU ARM7 128K HS FLASH 128-LQFP
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7L128-AU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
36MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.55 V ~ 1.8 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-LQFP
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
6 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
36 MHz
Number Of Programmable I/os
80
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Controller Family/series
AT91SAM7xxxx
No. Of I/o's
80
Ram Memory Size
6KB
Cpu Speed
36MHz
No. Of Timers
1
Rohs Compliant
Yes
Package
128LQFP
Device Core
ARM7TDMI
Family Name
91S
Maximum Speed
36 MHz
Operating Supply Voltage
2.5|3.3 V
For Use With
AT91SAM7L-STK - KIT EVAL FOR AT91SAM7LAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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19.3.2
19.3.2.1
Figure 19-2. Code Read Optimization in ARM Mode for FWS = 0
Note:
6257A–ATARM–20-Feb-08
Buffer 0 (128bits)
Buffer 1 (128bits)
Data To ARM
ARM Request
Flash Access
Master Clock
(32-bit)
When FWS is equal to 0, all the accesses are performed in a single-cycle access.
Read Operations
Code Read Optimization
@Byte 0
XXX
XXX
Bytes 0-15
An optimized controller manages embedded Flash reads, thus increasing performance when the
processor is running in ARM and Thumb mode by means of the 128-bit wide memory interface.
The Flash memory is accessible through 8-, 16- and 32-bit reads.
As the Flash block size is smaller than the address space reserved for the internal memory area,
the embedded Flash wraps around the address space and appears to be repeated within it.
The read operations can be performed with or without wait states. Wait states must be pro-
grammed in the field FWS (Flash Read Wait State) in the Flash Mode Register (MC_FMR).
Defining FWS to be 0 enables the single-cycle access of the embedded Flash. Refer to the Elec-
trical Characteristics for more details.
A system of 2 x 128-bit buffers is added in order to optimize sequential Code Fetch.
Note:
@Byte 4
Bytes 0-3
XXX
Immediate consecutive code read accesses are not mandatory to benefit from this optimization.
Bytes 16-31
@Byte 8
Bytes 4-7
@Byte 12
Bytes 8-11
Bytes 0-15
@Byte 16
Bytes 12-15
AT91SAM7L128/64 Preliminary
Bytes 32-47
@Byte 20
Bytes 16-19
Bytes 16-31
@Byte 24
Bytes 20-23
Bytes 24-27
@Byte 28
Bytes 32-47
@Byte 32
Bytes 28-31
143
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