ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 208
![MCU AVR 256KB FLASH A3B 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATXMEGA256A3B-MH
Manufacturer Part Number
ATXMEGA256A3B-MH
Description
MCU AVR 256KB FLASH A3B 64-QFN
Manufacturer
Atmel
Series
AVR® XMEGAr
Specifications of ATXMEGA256A3B-MH
Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
49
Program Memory Size
256KB (128K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 16x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATXMEGA256x
Core
AVR8
Data Bus Width
8 bit, 16 bit
Data Ram Size
16 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
49
Number Of Timers
7
Operating Supply Voltage
1.6 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
12 bit, 2 Channel
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATXMEGA256A3B-MU
ATXMEGA256A3B-MU
ATXMEGA256A3B-MU
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATXMEGA256A3B-MH
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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19.3.3
19.3.4
19.3.5
19.3.6
8077H–AVR–12/09
Bit Transfer
Address Packet
Data Packet
Transaction
As illustrated by
period of the SCL line. Consequently the SDA value can only be changed during the low period
of the clock. This is ensured in hardware by the TWI module.
Figure 19-4. Data Validity
Combining bit transfers results in the formation of address and data packets. These packets
consist of 8 data bits (one byte) with the most significant bit transferred first, plus a single bit not-
acknowledge (NACK) or acknowledge (ACK) response. The addressed device signals ACK by
pulling the SCL line low, and NACK by leaving the line SCL high during the ninth clock cycle.
After the START condition, a 7-bit address followed by a read/write (R/W) bit is sent. This is
always transmitted by the Master. A slave recognizing its address will ACK the address by pull-
ing the data line low the next SCL cycle, while all other slaves should keep the TWI lines
released, and wait for the next START and address. The 7-bit address, the R/W bit and the
acknowledge bit combined is the address packet. Only one address packet for each START
condition is given, also when 10-bit addressing is used.
The R/W specifies the direction of the transaction. If the R/W bit is low, it indicates a Master
Write transaction, and the master will transmit its data after the slave has acknowledged its
address. Opposite, for a Master Read operation the slave will start to transmit data after
acknowledging its address.
Data packets succeed an address packet or another data packet. All data packets are nine bits
long, consisting of one data byte and an acknowledge bit. The direction bit in the previous
address packet determines the direction in which the data is transferred.
A transaction is the complete transfer from a START to a STOP condition, including any
Repeated START conditions in between. The TWI standard defines three fundamental transac-
tion modes: Master Write, Master Read, and combined transaction.
Figure 19-5
ing a START condition (S) followed by an address packet with direction bit set to zero
(ADDRESS+W).
SDA
SCL
illustrates the Master Write transaction. The master initiates the transaction by issu-
Figure 19-4
a bit transferred on the SDA line must be stable for the entire high
DATA
Valid
Change
Allowed
XMEGA A
208
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