ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 228
![MCU AVR 256KB FLASH A3B 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATXMEGA256A3B-MH
Manufacturer Part Number
ATXMEGA256A3B-MH
Description
MCU AVR 256KB FLASH A3B 64-QFN
Manufacturer
Atmel
Series
AVR® XMEGAr
Specifications of ATXMEGA256A3B-MH
Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
49
Program Memory Size
256KB (128K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 16x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATXMEGA256x
Core
AVR8
Data Bus Width
8 bit, 16 bit
Data Ram Size
16 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
49
Number Of Timers
7
Operating Supply Voltage
1.6 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
12 bit, 2 Channel
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATXMEGA256A3B-MU
ATXMEGA256A3B-MU
ATXMEGA256A3B-MU
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATXMEGA256A3B-MH
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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19.11 Register Summary - TWI
19.12 Register Summary - TWI Master
19.13 Register Summary - TWI Slave
19.14 Interrupt Vector Summary
Table 19-9.
8077H–AVR–12/09
Address
Address
Address
+0x00
+0x01
+0x08
+0x00
+0x01
+0x02
+0x03
+0x04
+0x05
+0x06
+0x00
+0x01
+0x02
+0x03
+0x04
+0x05
Offset
0x00
0x02
Name
Name
Name
ADDRMASK
MASTER
STATUS
STATUS
CTRLC
SLAVE
CTRLA
CTRLB
CTRLA
CTRLB
TWI Interrupt vectors and their word offset addresses
BAUD
ADDR
ADDR
CTRL
DATA
DATA
Source
SLAVE_vect
MASTER_vect
Bit 7
Bit 7
Bit 7
RIF
DIF
-
-
-
-
INTLVL[1:0]
INTLVL[1:0]
Bit 6
Bit 6
Bit 6
APIF
WIF
-
-
-
-
Interrupt Description
TWI Slave Interrupt vector
TWI Master Interrupt vector
CLKHOLD
CLKHOLD
Bit 5
Bit 5
Bit 5
RIEN
DIEN
-
-
-
-
ADDRMASK[7:1]
Offset address for TWI Master
Offset address for TWI Slave
RXACK
RXACK
Bit 4
Bit 4
Bit 4
APIEN
WIEN
-
-
-
-
ADDR[7:0]
ADDR[7:0]
BAUD[7:0]
DATA[7:0]
DATA[7:0]
ARBLOST
ENABLE
ENABLE
Bit 3
Bit 3
Bit 3
COLL
-
-
-
TIMEOUT[1:0]
BUSERR
BUSERR
ACKACT
ACKACT
Bit 2
Bit 2
Bit 2
PIEN
-
-
SDAHOLD
TPMEN
Bit 1
Bit 1
Bit 1
QCEN
DIR
-
BUSSTATE[1:0]
CMD[1:0]
CMD[1:0]
ADDREN
XMEGA A
Bit 0
EDIEN
Bit 0
SMEN
Bit 0
SMEN
AP
-
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