ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 273
![MCU AVR 256KB FLASH A3B 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATXMEGA256A3B-MH
Manufacturer Part Number
ATXMEGA256A3B-MH
Description
MCU AVR 256KB FLASH A3B 64-QFN
Manufacturer
Atmel
Series
AVR® XMEGAr
Specifications of ATXMEGA256A3B-MH
Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
49
Program Memory Size
256KB (128K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 16x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATXMEGA256x
Core
AVR8
Data Bus Width
8 bit, 16 bit
Data Ram Size
16 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
49
Number Of Timers
7
Operating Supply Voltage
1.6 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
12 bit, 2 Channel
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATXMEGA256A3B-MU
ATXMEGA256A3B-MU
ATXMEGA256A3B-MU
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATXMEGA256A3B-MH
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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24.7.2
24.8
8077H–AVR–12/09
SDRAM Configuration
Multiplexing Data with Address Byte 0 and 1
When the data byte and address byte 0 (AD[7:0]), and address byte 1 (A[15:8]) are multiplexed,
they are output from the same port, and the ALE1 and ALE2 signal from the device control the
external address latches.
Figure 24-7. Multiplexed SRAM LPC connection using ALE1 and ALE2
Chip Select 3 on the EBI can be configured from SDRAM operation, and the EBI must be config-
ured for 3-Port or 4-Port interface. The SDRAM can be configured for 4-bit or 8-bit data bus, and
4-Port interface must be used for 8-bit data bus. The SDRAM interface signals from the EBI to
the SDRAM is listed in
Table 24-2.
Signal
CS
WE
RAS
CAS
DQM
CKE
CLK
BA[1:0]
A[12:0]
A[10]
D[7:0]
SDRAM Interface signals
EBI
Description
Chip Select
Write Enable
Row Address Strobe
Column Address Strobe
Data Mask Signal/ Output Enable
Clock Enable
Clock
Bank Address
Address bus
Precharge
Data bus
Table 24-2 on page
A[19:16]
A[15:8]/
AD[7:0]
ALE1
ALE2
D
G
273.
Q
D
G
Q
D[7:0]
A[7:0]
A[15:8]
A[19:16]
SRAM
XMEGA A
273
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