P89LPC9361FDH,518 NXP Semiconductors, P89LPC9361FDH,518 Datasheet - Page 10
P89LPC9361FDH,518
Manufacturer Part Number
P89LPC9361FDH,518
Description
MCU 80C51 16KB FLASH 28TSSOP
Manufacturer
NXP Semiconductors
Series
LPC900r
Datasheet
1.P89LPC9351FA112.pdf
(94 pages)
Specifications of P89LPC9361FDH,518
Program Memory Type
FLASH
Program Memory Size
16KB (16K x 8)
Package / Case
28-TSSOP
Core Processor
8051
Core Size
8-Bit
Speed
18MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
26
Eeprom Size
512 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x8b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
P89LPC
Core
80C51
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
18 MHz
Number Of Programmable I/os
23
Number Of Timers
2
Operating Supply Voltage
2.4 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (8 bit, 4 Channel)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
935289566518
NXP Semiconductors
Table 3.
P89LPC9331_9341_9351_9361
Product data sheet
Symbol
P2.0 to P2.7
P2.0/ICB/DAC0
/AD03
P2.1/OCD/AD02
P2.2/MOSI
P2.3/MISO
P2.4/SS
P2.5/SPICLK
P2.6/OCA
P2.7/ICA
P3.0 to P3.1
P3.0/XTAL2/
CLKOUT
Pin description
Pin
PLCC28,
TSSOP28
1
2
13
14
15
16
27
28
9
…continued
Type Description
I/O
I/O
I
O
I
I/O
O
I
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
O
I/O
I
I/O
I/O
O
O
Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type. During reset
Port 2 latches are configured in the input only mode with the internal pull-up
disabled. The operation of Port 2 pins as inputs and outputs depends upon the port
configuration selected. Each port pin is configured independently. Refer to
7.16.1 “Port configurations”
All pins have Schmitt trigger inputs.
Port 2 also provides various special functions as described below:
P2.0 — Port 2 bit 0.
ICB — Input Capture B. (P89LPC9351/9361)
DAC0 — Digital-to-analog converter output.
AD03 — ADC0 channel 3 analog input.
P2.1 — Port 2 bit 1.
OCD — Output Compare D. (P89LPC9351/9361)
AD02 — ADC0 channel 2 analog input.
P2.2 — Port 2 bit 2.
MOSI — SPI master out slave in. When configured as master, this pin is output;
when configured as slave, this pin is input.
P2.3 — Port 2 bit 3.
MISO — When configured as master, this pin is input, when configured as slave,
this pin is output.
P2.4 — Port 2 bit 4.
SS — SPI Slave select.
P2.5 — Port 2 bit 5.
SPICLK — SPI clock. When configured as master, this pin is output; when
configured as slave, this pin is input.
P2.6 — Port 2 bit 6.
OCA — Output Compare A. (P89LPC9351/9361)
P2.7 — Port 2 bit 7.
ICA — Input Capture A. (P89LPC9351/9361)
Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type. During reset
Port 3 latches are configured in the input only mode with the internal pull-up
disabled. The operation of Port 3 pins as inputs and outputs depends upon the port
configuration selected. Each port pin is configured independently. Refer to
7.16.1 “Port configurations”
All pins have Schmitt trigger inputs.
Port 3 also provides various special functions as described below:
P3.0 — Port 3 bit 0.
XTAL2 — Output from the oscillator amplifier (when a crystal oscillator option is
selected via the flash configuration.
CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK -TRIM.6).
It can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or
external clock input, except when XTAL1/XTAL2 are used to generate clock source
for the RTC/system timer.
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 10 January 2011
8-bit microcontroller with accelerated two-clock 80C51 core
P89LPC9331/9341/9351/9361
and
and
Table 12 “Static characteristics”
Table 12 “Static characteristics”
© NXP B.V. 2011. All rights reserved.
for details.
for details.
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