P89LPC9361FDH,518 NXP Semiconductors, P89LPC9361FDH,518 Datasheet - Page 82
P89LPC9361FDH,518
Manufacturer Part Number
P89LPC9361FDH,518
Description
MCU 80C51 16KB FLASH 28TSSOP
Manufacturer
NXP Semiconductors
Series
LPC900r
Datasheet
1.P89LPC9351FA112.pdf
(94 pages)
Specifications of P89LPC9361FDH,518
Program Memory Type
FLASH
Program Memory Size
16KB (16K x 8)
Package / Case
28-TSSOP
Core Processor
8051
Core Size
8-Bit
Speed
18MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
26
Eeprom Size
512 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x8b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
P89LPC
Core
80C51
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
18 MHz
Number Of Programmable I/os
23
Number Of Timers
2
Operating Supply Voltage
2.4 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (8 bit, 4 Channel)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
935289566518
NXP Semiconductors
Table 16.
V
T
P89LPC9331_9341_9351_9361
Product data sheet
Symbol
t
t
t
VR
RH
RL
amb
Fig 46. SPI slave timing (CPHA = 1)
DD
= 2.4 V to 3.6 V, unless otherwise specified.
=
−
40
°
Dynamic characteristics, ISP entry mode
C to +85
Parameter
V
time
RST HIGH time
RST LOW time
(CPOL = 0)
(CPOL = 1)
DD
11.2 ISP entry mode
SPICLK
SPICLK
(output)
active to RST active delay
(input)
(input)
(input)
MISO
MOSI
t
SPIA
SS
°
C for industrial applications,
Fig 47. ISP entry waveform
t
SPILEAD
t
t
SPIOH
SPIF
t
not defined
t
SPIF
SPIDV
V
t
t
RST
SPICLKH
SPICLKL
All information provided in this document is subject to legal disclaimers.
t
DD
SPIF
t
SPIDSU
slave MSB/LSB out
MSB/LSB in
T
SPICYC
Rev. 5 — 10 January 2011
Conditions
pin RST
pin RST
pin RST
−
t
SPIOH
t
t
40
t
SPICLKH
t
SPICLKL
SPIDV
SPIDH
8-bit microcontroller with accelerated two-clock 80C51 core
t
SPIR
°
C to +125
t
P89LPC9331/9341/9351/9361
VR
t
RL
t
SPIR
°
t
RH
C extended, unless otherwise specified.
t
SPIOH
t
SPIDV
Min
50
1
1
t
SPIDSU
slave LSB/MSB out
LSB/MSB in
Typ
-
-
-
t
t
SPIDH
SPILAG
002aaa911
002aaa912
t
SPIR
Max
-
32
-
© NXP B.V. 2011. All rights reserved.
t
SPIDIS
Unit
μs
μs
μs
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