P89LPC9351FA,529 NXP Semiconductors, P89LPC9351FA,529 Datasheet - Page 49

IC 80C51 MCU FLASH 8K 28-PLCC

P89LPC9351FA,529

Manufacturer Part Number
P89LPC9351FA,529
Description
IC 80C51 MCU FLASH 8K 28-PLCC
Manufacturer
NXP Semiconductors
Series
LPC900r
Datasheet

Specifications of P89LPC9351FA,529

Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
28-PLCC
Core Processor
8051
Core Size
8-Bit
Speed
18MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
26
Eeprom Size
512 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x8b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
P89LPC
Core
80C51
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
18 MHz
Number Of Programmable I/os
23
Number Of Timers
2
Operating Supply Voltage
2.4 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
OM11004 - KIT IAR KICKSTART LPC935568-1758 - BOARD EVAL FOR LPC93X MCU FAMILY
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
935287627529

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
P89LPC9351FA,529
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
P89LPC9331_9341_9351_9361
Product data sheet
Fig 16. SPI block diagram
SPI STATUS REGISTER
BY 4, 16, 64, 128
CPU clock
DIVIDER
SELECT
SPI CONTROL
7.25 SPI
The P89LPC9331/9341/9351/9361 provides another high-speed serial communication
interface: the SPI interface. SPI is a full-duplex, high-speed, synchronous communication
bus with two operation modes: Master mode and Slave mode. Up to 3 Mbit/s can be
supported in either Master mode or Slave mode. It has a Transfer Completion Flag and
Write Collision Flag Protection.
The SPI interface has four pins: SPICLK, MOSI, MISO and SS:
Typical connections are shown in
SPICLK, MOSI and MISO are typically tied together between two or more SPI
devices. Data flows from master to slave on MOSI (Master Out Slave In) pin and flows
from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal is output
in the Master mode and is input in the Slave mode. If the SPI system is disabled, i.e.,
SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port functions.
SS is the optional slave select pin. In a typical configuration, an SPI master asserts
one of its port pins to select one SPI device as the current slave. An SPI slave device
uses its SS pin to determine whether it is selected.
interrupt
request
SPI clock (master)
SPI
MSTR
SPEN
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 10 January 2011
internal
data
bus
8-bit microcontroller with accelerated two-clock 80C51 core
SPI CONTROL REGISTER
P89LPC9331/9341/9351/9361
8-BIT SHIFT REGISTER
READ DATA BUFFER
CLOCK LOGIC
Figure 17
clock
through
Figure
19.
M
M
M
S
S
S
CONTROL
LOGIC
PIN
© NXP B.V. 2011. All rights reserved.
002aaa900
MISO
P2.3
MOSI
P2.2
SPICLK
P2.5
SS
P2.4
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