Z8F6421AN020EC00TR Zilog, Z8F6421AN020EC00TR Datasheet - Page 178
Z8F6421AN020EC00TR
Manufacturer Part Number
Z8F6421AN020EC00TR
Description
IC ENCORE MCU FLASH 64K 44LQFP
Manufacturer
Zilog
Series
Encore!® XP®r
Specifications of Z8F6421AN020EC00TR
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
31
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
44-LQFP
For Use With
269-4678 - KIT DEV FOR Z8F642 MCU 44 PIN269-4677 - KIT DEV FOR Z8F642 MCU 28PIN269-4540 - KIT DEV FOR Z8 ENCORE 16K TO 64K
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
Z8F6421AN020EC00T
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PS019921-0308
DMAx I/O Address Register
1 = DMAx, after the End Address data is transferred, reloads the original Start
DDIR—DMAx Data Transfer Direction
0 = Register File → on-chip peripheral control register.
1 = on-chip peripheral control register → Register File.
IRQEN—DMAx Interrupt Enable
0 = DMAx does not generate any interrupts.
1 = DMAx generates an interrupt when the End Address data is transferred.
WSEL—Word Select
0 = DMAx transfers a single byte per request.
1 = DMAx transfers a two-byte word per request. The address for the on-chip
RSS—Request Trigger Source Select
The Request Trigger Source Select field determines the peripheral that can initiate a DMA
transfer. The corresponding interrupts do not need to be enabled within the Interrupt Con-
troller to initiate a DMA transfer. However, if the Request Trigger Source can enable or
disable the interrupt request sent to the Interrupt Controller, the interrupt request must be
enabled within the Request Trigger Source block.
000 = Timer 0.
001 = Timer 1.
010 = Timer 2.
011 = Timer 3.
100 = DMA0 Control register: UART0 Received Data register contains valid data.
101 = DMA0 Control register: UART1 Received Data register contains valid data. DMA1
Control register: UART1 Transmit Data register empty.
110 = DMA0 Control register: I
111 = Reserved.
The DMAx I/O Address register
address for data transfer. The full 12-bit Register File address is given by {FH,
Address and continues operating.
peripheral control register must be an even address.
DMA1 Control register: UART0 Transmit Data register empty.
Transmitter Interrupt register empty.
2
(Table
C Receiver Interrupt. DMA1 Control register: I
78) contains the low byte of the on-chip peripheral
Z8 Encore! XP
Direct Memory Access Controller
Product Specification
®
F64XX Series
2
C
164
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