Z86E7216VSC00TR Zilog, Z86E7216VSC00TR Datasheet - Page 45

• Manufacturer Part Number: Z86E7216VSC00TR
• Description: IC MCU OTP 16K ZIRC 44PLCC
• Manufacturer: Zilog
• Series: Z8®r

Specifications of Z86E7216VSC00TR

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 16MHz
• Peripherals: LVD, POR, WDT
• Number Of I /o: 31
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 748 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

PS008704-0507
*
*
U = Unknown
Working Register
** All addresses are in hexadecimal.
† Not reset with a Stop-Mode Recovery, except Bit 0.
(0) 03
(0) 02
(0) 01
(0) 00
* Not reset with a Stop-Mode Recovery
EXPANDED REG. GROUP (0)
REGISTER**
Group Pointer
FF
F0
7F
0F
00
7 6 5 4 3 2 1 0
Z8 Register File (Bank 0)**
REGISTER POINTER
P3
P2
P1
P0
U U U U U U U U
U
0
U U U U U U U U
Expanded Register
Bank Group Pointer
RESET CONDITION
U
0
U
0
Reserved
U
0
U
U
Reserved
U
U
U
U
U
U
*
*
†
*
*
Z8 Standard Control Registers
REGISTER**
EXPANDED REG. BANK/GROUP (F)
REGISTER**
EXPANDED REG. BANK/GROUP (D)
REGISTER**
FD
FC
FE
FB
FF
FA
F9
F8
F7
F6
F5
F4
F3
F2
F1
F0
(F) 0D
(F) 0C
(D) 0C
(F) 0F
(F) 0E
(F) 0B
(F) 0A
(D) 0B
(D) 0A
(F) 09
(F) 08
(F) 07
(F) 06
(F) 05
(F) 04
(F) 03
(F) 02
(F) 01
(F) 00
(D) 09
(D) 08
(D) 07
(D) 06
(D) 05
(D) 04
(D) 03
(D) 02
(D) 01
(D) 00
SPL
SPH
RP
FLAGS
IMR
IRQ
IPR
P01M
P3M
P2M
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
HI8
LO8
HI16
LO16
TC16H
TC16L
TC8H
TC8L
Reserved
CTR2
CTR1
CTR0
WDTMR
Reserved
SMR2
Reserved
SMR
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PCON
OTP Microcontroller
D7 D6 D5 D4 D3 D2 D1 D0
U
U
0
U
0
0
U
0
0
1
U
U
U
U
0
0
U
U
U U U U U U U 0
U
U
U
U
U
U
U
U
0
0
0
0
0 0 0 0 0 0 0 0
RESET CONDITION
RESET CONDITION
U
U
0
U
U
0
U
1
0
1
U
U
U
U
0
U
U
U
U
U
U
U
U
U
U
U
0
0
0
0
RESET CONDITION
U
U
0
U
U
0
U
0
0
1
U
U
U
U
0
U
U
U
U
U
U
U
U
U
U
U
U
U
U
1
U
U
U
U
U
U
U
U
U
U
U
U
U
0
U
U
0
U
0
0
1
U
U
U
U
0
0
0
0
0
U
U
0
U
U
0
U
1
0
1
U
U
U
U
0
0
1
0
0
U
U
U
U
U
U
U
U
U
U
U
U
U
0
U
U
0
U
1
0
1
U
U
U
U
0
0
U
U
U
U
U
U
U
U
U
U
U
1
0
0
U
U
0
U
U
0
U
0
0
1
U
U
U
U
0
0
U
U
U
U
U
U
U
U
U
U
U
U
U
0
U
U
U
U
U
U
U
U
U
0
U
U
0
U
U
0
U
1
0
1
U
U
U
U
0
0
U
1
0
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