MC908QY2AMPE Freescale Semiconductor, MC908QY2AMPE Datasheet - Page 121
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MC908QY2AMPE
Manufacturer Part Number
MC908QY2AMPE
Description
IC MCU 8BIT 1.5K FLASH 16DIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908QT1ACDWE.pdf
(200 pages)
Specifications of MC908QY2AMPE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, PWM
Number Of I /o
13
Program Memory Size
1.5KB (1.5K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
16-DIP (0.300", 7.62mm)
Processor Series
HC08QY
Core
HC08
Data Bus Width
8 bit
Data Ram Size
128 B
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
13
Number Of Timers
2
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
Minimum Operating Temperature
- 40 C
On-chip Adc
6-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908QY2AMPE
Manufacturer:
Freescale Semiconductor
Quantity:
135
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In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the
module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.
Wait mode can also be exited by a reset (or break in emulation mode). A break interrupt during wait mode
sets the SIM break stop/wait bit, SBSW, in the break status register (BSR). If the COP disable bit, COPD,
in the configuration register is 0, then the computer operating properly module (COP) is enabled and
remains active in wait mode.
Figure 13-15
13.7.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a
module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the oscillator signals (BUSCLKX2 and BUSCLKX4) in stop mode, stopping the CPU
and peripherals. If OSCENINSTOP is set, BUSCLKX2 will remain running in STOP and can be used to
run the AWU. Stop recovery time is selectable using the SSREC bit in the configuration register 1
(CONFIG1). If SSREC is set, stop recovery is reduced from the normal delay of 4096 BUSCLKX4 cycles
down to 32. This is ideal for the internal oscillator, RC oscillator, and external oscillator options which do
not require long start-up times from stop mode.
Freescale Semiconductor
and
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt
ADDRESS BUS
ADDRESS BUS
1. RST is only available if the RSTEN bit in the CONFIG1 register is set.
External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
BUSCLKX4
DATA BUS
DATA BUS
Figure 13-16
RST
(1)
Figure 13-16. Wait Recovery from Internal Reset
$A6
$A6
Figure 13-15. Wait Recovery from Interrupt
MC68HC908QYA/QTA Family Data Sheet, Rev. 3
show the timing for wait recovery.
$6E0B
$A6
$6E0B
$A6
$A6
$A6
CYCLES
$6E0C
32
NOTE
$01
$00FF
CYCLES
$0B
32
$00FE
$6E
RST VCT H
$00FD
RST VCT L
$00FC
Low-Power Modes
121
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