TMP86FS28DFG(JZ) Toshiba, TMP86FS28DFG(JZ) Datasheet - Page 177
TMP86FS28DFG(JZ)
Manufacturer Part Number
TMP86FS28DFG(JZ)
Description
IC MCU 8BIT FLASH 60KB 80-LQFP
Manufacturer
Toshiba
Series
TLCS-870/Cr
Datasheet
1.TMP86FS28DFGJZ.pdf
(272 pages)
Specifications of TMP86FS28DFG(JZ)
Core Processor
870/C
Core Size
8-Bit
Speed
16MHz
Connectivity
SIO, UART/USART
Peripherals
LCD, PWM, WDT
Number Of I /o
62
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-LQFP
Processor Series
TLCS-870
Core
870/C
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SIO, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
62
Number Of Timers
6
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
BM1040R0A, BMP86A100010A, BMP86A100010B, BMP86A200010B, BMP86A200020A, BMP86A300010A, BMP86A300020A, BMP86A300030A, SW89CN0-ZCC, SW00MN0-ZCC
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
BM1401W0A-G - FLASH WRITER ON-BOARD PROGRAMTMP89C900XBG - EMULATION CHIP TMP89F LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
TMP86FS28DFGJZ
Available stocks
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Part Number
Manufacturer
Quantity
Price
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12.4 Transfer Rate
12.5 Data Sampling Method
RXD1 pin
RXD1 pin
RT clock
Internal receive data
RT clock
Internal receive data
rate are determined as follows:
detected in RXD1 pin input. RT clock starts detecting “L” level of the RXD1 pin. Once a start bit is detected, the
start bit, data bits, stop bit(s), and parity bit are sampled at three times of RT7, RT8, and RT9 during one receiver
clock interval (RT clock). (RT0 is the position where the bit supposedly starts.) Bit is determined according to major-
ity rule (The data are the same twice or more out of three samplings).
The baud rate of UART1 is set of UART1CR1<BRG>. The example of the baud rate are shown as follows.
When TC5 is used as the UART1 transfer rate (when UART1CR1<BRG> = “110”), the transfer clock and transfer
Transfer clock [Hz] = TC5 source clock [Hz] / TTREG5 setting value
Transfer Rate [baud] = Transfer clock [Hz] / 16
The UART1 receiver keeps sampling input using the clock selected by UART1CR1<BRG> until a start bit is
Table 12-1 Transfer Rate (Example)
BRG
000
001
010
100
101
011
RT0 1
RT0 1
Figure 12-4 Data Sampling Method
76800 [baud]
Start bit
Start bit
Start bit
Start bit
16 MHz
38400
19200
9600
4800
2400
2
2
3 4
3 4
5 6
5 6
(a) Without noise rejection circuit
(b) With noise rejection circuit
Page 165
7
7
8 9 10 11 12 13 14 15 0
8 9 10 11 12 13 14 15 0
38400 [baud]
Source Clock
8 MHz
19200
9600
4800
2400
1200
Bit 0
Bit 0
Bit 0
Bit 0
1
1
2 3
2 3
19200 [baud]
4 MHz
9600
4800
2400
1200
600
4 5
4 5
6
6
7 8
7 8
TMP86FS28DFG
9 10 11
9 10 11
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