TMP86FS28DFG(JZ) Toshiba, TMP86FS28DFG(JZ) Datasheet - Page 48

• Manufacturer Part Number: TMP86FS28DFG(JZ)
• Description: IC MCU 8BIT FLASH 60KB 80-LQFP
• Manufacturer: Toshiba
• Series: TLCS-870/Cr

Specifications of TMP86FS28DFG(JZ)

• Core Processor: 870/C
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Processor Series: TLCS-870
• Core: 870/C
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SIO, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 62
• Number Of Timers: 6
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: BM1040R0A, BMP86A100010A, BMP86A100010B, BMP86A200010B, BMP86A200020A, BMP86A300010A, BMP86A300020A, BMP86A300030A, SW89CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: BM1401W0A-G - FLASH WRITER ON-BOARD PROGRAMTMP89C900XBG - EMULATION CHIP TMP89F LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: TMP86FS28DFGJZ

3.1 Interrupt latches (IL29 to IL2)
Example 1 :Clears interrupt latches
Example 2 :Reads interrupt latchess
Example 3 :Tests interrupt latches
3.1 Interrupt latches (IL29 to IL2)
3.2 Interrupt enable register (EIR)
3.2.1 Interrupt master enable flag (IMF)
fined instruction interrupt. When interrupt request is generated, the latch is set to “1”, and the CPU is requested to
accept the interrupt if its interrupt is enabled. The interrupt latch is cleared to "0" immediately after accepting inter-
rupt. All interrupt latches are initialized to “0” during reset.
cleared to "0" individually by instruction. However, IL2 and IL3 should not be cleared to "0" by software. For clear-
ing the interrupt latch, load instruction should be used and then IL2 and IL3 should be set to "1". If the read-modify-
write instructions such as bit manipulation or operation instructions are used, interrupt request would be cleared
inadequately if interrupt is requested while such instructions are executed.
interrupts (Software interrupt, undefined instruction interrupt, address trap interrupt and watchdog interrupt). Non-
maskable interrupt is accepted regardless of the contents of the EIR.
registers are located on address 002CH, 002DH, 003AH and 003BH in SFR area, and they can be read and written
by an instructions (Including read-modify-write instructions such as bit manipulation or operation instructions).
An interrupt latch is provided for each interrupt source, except for a software interrupt and an executed the unde-
The interrupt latches are located on address 002EH, 002FH, 003CH and 003DH in SFR area. Each latch can be
Interrupt latches are not set to “1” by an instruction.
Since interrupt latches can be read, the status for interrupt requests can be monitored by software.
Note: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to
The interrupt enable register (EIR) enables and disables the acceptance of interrupts, except for the non-maskable
The EIR consists of an interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). These
While IMF = “0”, all maskable interrupts are not accepted regardless of the status on each individual interrupt
enable flag (EF). By setting IMF to “1”, the interrupt becomes acceptable if the individuals are enabled. When
an interrupt is accepted, IMF is cleared to “0” after the latest status on IMF is stacked. Thus the maskable inter-
rupts which follow are disabled. By executing return interrupt instruction [RETI/RETN], the stacked data,
which was the status before interrupt acceptance, is loaded on IMF again.
The IMF is normally set and cleared by [EI] and [DI] instruction respectively. During reset, the IMF is initial-
ized to “0”.
"0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL
(Enable interrupt by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on
interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL
should be executed before setting IMF="1".
The interrupt enable register (IMF) enables and disables the acceptance of the whole maskable interrupt.
The IMF is located on bit0 in EIRL (Address: 003AH in SFR), and can be read and written by an instruction.
DI
LDW
EI
LD
TEST
JR
(ILL), 1110100000111111B
WA, (ILL)
(ILL). 7
F, SSET
Page 36
; IMF
; IL12, IL10 to IL6
; IMF
; W
; if IL7 = 1 then jump
←
←
←
ILH, A
0
1
←
←
ILL
0
TMP86FS28DFG