S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 199
S9S12XS256J0CAL
Manufacturer Part Number
S9S12XS256J0CAL
Description
MCU 256K FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12XS64CAE.pdf
(738 pages)
Specifications of S9S12XS256J0CAL
Core Processor
HCS12X
Core Size
16-Bit
Speed
40MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
8K x 8
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12XS
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
12 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
91
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
DEMO9S12XSFAME, EVB9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
S9S12XS256J0CAL
Manufacturer:
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Quantity:
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6.3.2.2
Read: Anytime
Write: Never
Freescale Semiconductor
Address: 0x0021
DBGBRK
SSF[2:0]
COMRV
Reset
Field
Field
POR
TBF
1–0
2–0
3
7
W
R
S12XDBG Breakpoint Enable Bit — The DBGBRK bit controls whether the debugger will request a breakpoint
to S12XCPU upon reaching the state sequencer Final State. If tracing is enabled, the breakpoint is generated
on completion of the tracing session. If tracing is not enabled, the breakpoint is generated immediately. Please
refer to
0 No breakpoint on trigger.
1 Breakpoint on trigger
Comparator Register Visibility Bits — These bits determine which bank of comparator register is visible in the
8-byte window of the S12XDBG module address map, located between 0x0028 to 0x002F. Furthermore these
bits determine which register is visible at the address 0x0027. See
Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was
last armed. If this bit is set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits CNT[6:0].
The TBF bit is cleared when ARM in DBGC1 is written to a one. The TBF is cleared by the power on reset
initialization. Other system generated resets have no affect on this bit
State Sequencer Flag Bits — The SSF bits indicate in which state the State Sequencer is currently in. During
a debug session on each transition to a new state these bits are updated. If the debug session is ended by
software clearing the ARM bit, then these bits retain their value to reflect the last state of the state sequencer
before disarming. If a debug session is ended by an internal trigger, then the state sequencer returns to state0
and these bits are cleared to indicate that state0 was entered during the session. On arming the module the state
sequencer enters state1 and these bits are forced to SSF[2:0] = 001. See
TBF
Debug Status Register (DBGSR)
—
0
7
COMRV
Section 6.4.7
00
01
10
11
= Unimplemented or Reserved
0
0
6
0
Table 6-4. DBGC1 Field Descriptions (continued)
for further details.
Figure 6-4. Debug Status Register (DBGSR)
Visible Comparator
S12XS Family Reference Manual, Rev. 1.11
Table 6-6. DBGSR Field Descriptions
Comparator A
Comparator B
Comparator C
Comparator D
0
0
0
5
Table 6-5. COMRV Encoding
0
0
0
4
Description
Description
Visible Register at 0x0027
0
0
0
3
Table
DBGSCR1
DBGSCR2
DBGSCR3
DBGMFR
SSF2
6-5.
Table 6-7
0
0
2
S12X Debug (S12XDBGV3) Module
.
SSF1
0
0
1
SSF0
0
0
0
199
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