R5F21324ANSP#U1 Renesas Electronics America, R5F21324ANSP#U1 Datasheet - Page 439
R5F21324ANSP#U1
Manufacturer Part Number
R5F21324ANSP#U1
Description
MCU 1KB FLASH 16K ROM 20-LSSOP
Manufacturer
Renesas Electronics America
Series
R8C/3x/32Ar
Datasheet
1.R5F21322ANSPU1.pdf
(629 pages)
Specifications of R5F21324ANSP#U1
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
15
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
20-LSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Under development
R8C/32A Group
REJ09B0458-0020 Rev.0.20
Page 409 of 583
25.4.3
In master receive mode, the master device outputs the receive clock, receives data from the slave device, and
returns an acknowledge signal.
Figures 25.7 and 25.8 show the Operating Timing in Master Receive Mode (I
The receive procedure and operation in master receive mode are shown below.
(1) After setting the TEND bit in the ICSR register to 0, set the TRS bit in the ICCR1 register to 0 to switch
(2) Dummy reading the ICDRR register starts receive operation. The receive clock is output in synchronization
(3) When 1-frame of data reception is completed, the RDRF bit in the ICSR register is set to 1 at the rising
(4) Continuous receive operation is enabled by reading the ICDRR register every time the RDRF bit is set to 1.
(5) If the next frame is the last receive frame and the RCVD bit in the ICCR1 register is set to 1 (next receive
(6) When the RDRF bit is set to 1 at the rising edge of the 9th clock cycle of the receive clock, generate a stop
(7) When the STOP bit in the ICSR register is set to 1, read the ICDRR register and set the RCVD bit to 0 (next
(8) Return to slave receive mode.
from master transmit mode to master receive mode. Then set the TDRE bit in the ICSR register to 0.
with the internal clock and data is received. The master device outputs the level set by the ACKBT bit in
the ICIER register to the SDA pin at the rising edge of the 9th clock cycle of the receive clock.
edge of the 9th clock cycle of the receive clock. At this time, if the ICDRR register is read, the received
data can be read and the RDRF bit is set to 0 simultaneously.
If reading the ICDRR register is delayed by another process and the 8th clock cycle falls while the RDRF
bit is set to 1, the SCL signal is fixed “L” until the ICDRR register is read.
operation disabled) before reading the ICDRR register, stop condition generation is enabled after the next
receive operation.
condition.
receive operation continues).
Master Receive Operation
Preliminary specification
Specifications in this manual are tentative and subject to change.
Nov 05, 2008
2
C bus Interface Mode).
25. I
2
C bus Interface
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