R5F21324ANSP#U1 Renesas Electronics America, R5F21324ANSP#U1 Datasheet - Page 468
R5F21324ANSP#U1
Manufacturer Part Number
R5F21324ANSP#U1
Description
MCU 1KB FLASH 16K ROM 20-LSSOP
Manufacturer
Renesas Electronics America
Series
R8C/3x/32Ar
Datasheet
1.R5F21322ANSPU1.pdf
(629 pages)
Specifications of R5F21324ANSP#U1
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
15
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
20-LSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Under development
R8C/32A Group
REJ09B0458-0020 Rev.0.20
Page 438 of 583
Figure 26.9
26.4.3
LINCR register
TRAIC register
BCDCT flag in
LINST register
Transfer clock
U0C1 register
LINE bit in
RXD0 pin
TXD0 pin
The bus collision detection function can be used if UART0 is enabled for transmission (TE bit in U0C1 register
= 1). To detect a bus collision during Synch Break transmission, set the BCE bit in the LINCR2 register to 1
(bus collision detection enabled).
Figure 26.9 shows an Operating Example When Bus Collision is Detected.
TE bit in
IR bit in
Bus Collision Detection Function
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Preliminary specification
Specifications in this manual are tentative and subject to change.
Operating Example When Bus Collision is Detected
Set to 1 by a program.
Set to 1 by a program.
Nov 05, 2008
Set to 0 when an interrupt request is acknowledged
or by a program.
1 is written to B2CLR bit in LINST register.
26. Hardware LIN
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